|
|
| Jan Staschulat and Rolf Ernst, "Worst case timing analysis of input dependent data cache behavior," in Euromicro Conference on Real-Time Systems (ECRTS), (Dresden, Germany), July 2006 |  |
 | | | @inproceedings{SE06:Worsttiminanalyinput, ADDRESS = "Dresden, Germany",
AUTHOR = "Jan Staschulat and Rolf Ernst",
BOOKTITLE = "Euromicro Conference on Real-Time Systems (ECRTS)",
MONTH = "jul",
TITLE = "Worst case timing analysis of input dependent data cache behavior",
YEAR = "2006",
} | | Simon Schliecker, Matthias Ivers, Jan Staschulat, und Rolf Ernst, "A Framework for the Busy Time Calculation of Multiple Correlated Events," in 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, No. 06902, (Dresden, Germany), July 2006 | |
|  | | @inproceedings{SIS+06:FrameCalcuMultiCorre, ADDRESS = "Dresden, Germany",
AUTHOR = "Simon Schliecker and Matthias Ivers and Jan Staschulat and Rolf Ernst",
BOOKTITLE = "6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis",
MONTH = "jul",
NUMBER = "06902",
TITLE = "A Framework for the Busy Time Calculation of Multiple Correlated Events",
YEAR = "2006",
} | | Jan Staschulat, Simon Schliecker, und Rolf Ernst, "Scheduling Analysis of Real-time Systems with Precise Modeling of Cache Related Preemption Delay," in Euromicro Conference on Real-Time Systems (ECRTS), (Palma de Mallorca, Spain), July 2005 | | | | | @inproceedings{SSE05:SchedAnalyRealtSyste, ADDRESS = "Palma de Mallorca, Spain",
AUTHOR = "Jan Staschulat and Simon Schliecker and Rolf Ernst",
BOOKTITLE = "Euromicro Conference on Real-Time Systems (ECRTS)",
MONTH = "jul",
TITLE = "Scheduling Analysis of Real-time Systems with Precise Modeling of Cache Related Preemption Delay",
YEAR = "2005",
} | | Jan Staschulat, Simon Schliecker, Matthias Ivers, und Rolf Ernst, "Analysis of Memory Latencies in Multi-Processor Systems," in 5th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, (Palma de Mallorca, Spain), July 2005 | |
| | | @inproceedings{SSI+05:AnalyMemorLatenMulti, ADDRESS = "Palma de Mallorca, Spain",
AUTHOR = "Jan Staschulat and Simon Schliecker and Matthias Ivers and Rolf Ernst",
BOOKTITLE = "5th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis",
MONTH = "jul",
TITLE = "Analysis of Memory Latencies in Multi-Processor Systems",
YEAR = "2005",
} | | Jan Staschulat and Rolf Ernst, "Scalable Precision Cache Analysis for Preemptive Scheduling," in Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), (Chicago, USA), June 2005 | |
| | | @inproceedings{SE05:ScalaPreciCacheAnaly, ADDRESS = "Chicago, USA",
AUTHOR = "Jan Staschulat and Rolf Ernst",
BOOKTITLE = "Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES)",
MONTH = "jun",
TITLE = "Scalable Precision Cache Analysis for Preemptive Scheduling",
YEAR = "2005",
} | | Jan Staschulat, Rolf Ernst, Andreas Schulze, und Fabian Wolf, "Context Sensitive Performance Analysis of Automotive Applications," in Designer's Forum at Design, Automation and Test in Europe (DATE), March 2005 | |
| | | @inproceedings{SES+05:ConteSensiPerfoAnaly, AUTHOR = "Jan Staschulat and Rolf Ernst and Andreas Schulze and Fabian Wolf",
BOOKTITLE = "Designer's Forum at Design, Automation and Test in Europe (DATE)",
MONTH = "mar",
TITLE = "Context Sensitive Performance Analysis of Automotive Applications",
YEAR = "2005",
} | Simon Schliecker, "Schedulinganalyse unter Berücksichtigung variabler cacheabhängiger Unterbrechungskosten," Diplomarbeit, Institute for Computer and Communication Network Engineering, Braunschweig, Germany, October 2004
IDA-Signatur: DPA 3450 | | | | | @mastersthesis{Sch04:SchedunterBerckvaria, ADDRESS = "Braunschweig, Germany",
AUTHOR = "Simon Schliecker",
MONTH = "oct",
SCHOOL = "Institute for Computer and Communication Network Engineering",
TITLE = "Schedulinganalyse unter Berücksichtigung variabler cacheabhängiger Unterbrechungskosten",
TYPE = "Diplomarbeit",
YEAR = "2004",
} | | Jan Staschulat and Rolf Ernst, "Multiple Process Execution in Cache Related Preemption Delay Analysis," in ACM International Conference on Embedded Software (EMSOFT), (Pisa, Italy), pp. 278-286, September 2004 | |
| | | @inproceedings{SE04:MultiProceExecuCache, ADDRESS = "Pisa, Italy",
AUTHOR = "Jan Staschulat and Rolf Ernst",
BOOKTITLE = "ACM International Conference on Embedded Software (EMSOFT)",
MONTH = "sep",
PAGES = "278--286",
TITLE = "Multiple Process Execution in Cache Related Preemption Delay Analysis",
YEAR = "2004",
} | | Jan Staschulat and Rolf Ernst, "Synergetic Effects in Cache Related Preemption Delays," in International Workhop on Worst-Case Execution Time Analysis, (Catania, Italy), pp. 37-40, IRISA, Publication Interne Nr 1645, June 2004 | |
| | | @inproceedings{SE04:SynerEffecCacheRelat, ADDRESS = "Catania, Italy",
AUTHOR = "Jan Staschulat and Rolf Ernst",
BOOKTITLE = "International Workhop on Worst-Case Execution Time Analysis",
MONTH = "jun",
PAGES = "37--40",
PUBLISHER = "IRISA, Publication Interne Nr 1645",
TITLE = "Synergetic Effects in Cache Related Preemption Delays",
YEAR = "2004",
} | | Jan Staschulat and Rolf Ernst, "CRPD Independence for multiple process execution." , March 2004 | |
| | | @misc{SE04:CRPD_IndepMultiProce, AUTHOR = "Jan Staschulat and Rolf Ernst",
HOWPUBLISHED = "Technical Report",
MONTH = "March",
TITLE = "CRPD Independence for multiple process execution",
YEAR = "2004",
} | | Jan Staschulat and Rolf Ernst, "Cache Effects in Multi Process Real-Time Systems with Preemptive Scheduling," Institut für Datentechnik und Kommunikationsnetze, TU Braunschweig, November 2003 | |
| | | @techreport{SE03:CacheEffecMultiProce, AUTHOR = "Jan Staschulat and Rolf Ernst",
INSTITUTION = "Institut für Datentechnik und Kommunikationsnetze, TU Braunschweig",
MONTH = "nov",
TITLE = "Cache Effects in Multi Process Real-Time Systems with Preemptive Scheduling",
YEAR = "2003",
} | | Marek Jersak, Kai Richter, Razvan Racu, Jan Staschulat, Rolf Ernst, Jörn Braam, und Fabian Wolf, "Formal methods for integration of automotive software in Embedded Software for SoC," in Embedded Software for SoC (Ahmed Jerraya and Sungjoo Yoo and Diederik Verkest, Ed.), chapter 2, pp. 11-24, Kluwer Academic Publishers, 2003 | | | | | @incollection{JRR+03:EmbedSoftwforSoC, AUTHOR = "Marek Jersak and Kai Richter and Razvan Racu and Jan Staschulat and Rolf Ernst and Jörn Braam and Fabian Wolf",
BOOKTITLE = "Embedded Software for SoC",
CHAPTER = "2",
EDITOR = "Ahmed Jerraya and Sungjoo Yoo and Diederik Verkest",
PAGES = "11--24",
PUBLISHER = "Kluwer Academic Publishers",
TITLE = "Formal methods for integration of automotive software in Embedded Software for SoC",
YEAR = "2003",
} | | F. Wolf, J. Staschulat, und R. Ernst, "Hybrid Cache Analysis in Running Time Verification of Embedded Software," Kluwer Journal of Design Automation for Embedded Systems, vol. 7, No. 3, pp. 271-295, October 2002 | |
| | | @article{WSE02:HybriCacheAnalyRunni, AUTHOR = "F. Wolf and J. Staschulat and R. Ernst",
JOURNAL = "Kluwer Journal of Design Automation for Embedded Systems",
MONTH = "oct",
NUMBER = "3",
PAGES = "271--295",
TITLE = "Hybrid Cache Analysis in Running Time Verification of Embedded Software",
VOLUME = "7",
YEAR = "2002",
} | | F. Wolf, J. Staschulat, und R. Ernst, "Associative Caches in Formal Software Timing Analysis," in Proceedings of the IEEE/ACM Design Automation Conference, New Orleans, June 2002 | |
| | | @inproceedings{WSE02:AssocCacheFormaSoftw, AUTHOR = "F. Wolf and J. Staschulat and R. Ernst",
BOOKTITLE = "Proceedings of the IEEE/ACM Design Automation Conference, New Orleans",
MONTH = "jun",
TITLE = "Associative Caches in Formal Software Timing Analysis",
YEAR = "2002",
} | | F. Wolf, J. Kruse, und R. Ernst, "Timing and Power Measurement in Static Software Analysis," Microelectronics Journal, Special Issue on Design, Modeling and Simulation in Microelectronics and MEMS, vol. 6, No. 2, pp. 91-100, January 2002 | |
| | | @article{WKE02:TiminPowerMeasuStati, AUTHOR = "F. Wolf and J. Kruse and R. Ernst",
JOURNAL = "Microelectronics Journal, Special Issue on Design, Modeling and Simulation in Microelectronics and {MEMS}",
MONTH = "January",
NUMBER = "2",
PAGES = "91--100",
TITLE = "Timing and Power Measurement in Static Software Analysis",
VOLUME = "6",
YEAR = "2002",
} | Fabian Wolf, "Behavioral Intervals in Embedded Software,", Kluwer Academic Publishers, 2002
IDA-Signatur: S 218 and S 218.1 and S 218.2 and S 218.3 | |
| | | @book{Wol02:BehavInterEmbedSoftw, AUTHOR = "Fabian Wolf",
PUBLISHER = "Kluwer Academic Publishers",
TITLE = "Behavioral Intervals in Embedded Software",
YEAR = "2002",
} | | F. Wolf, R. Ernst, und W. Ye, "Path Clustering in Software Timing Analysis," IEEE Transactions on VLSI Systems, vol. 9, No. 6, December 2001 | |
| | | @article{WEY01:PathClustSoftwTimin, AUTHOR = "F. Wolf and R. Ernst and W. Ye",
JOURNAL = "IEEE Transactions on VLSI Systems",
MONTH = "December",
NUMBER = "6",
TITLE = "Path Clustering in Software Timing Analysis",
VOLUME = "9",
YEAR = "2001",
} | | D. Ziegenbein, F. Wolf, K. Richter, M. Jersak, und R. Ernst, "Interval-Based Analysis Of Software Processes," in Proceedings Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES '2001), (Snowbird, Utah, USA), pp. 94-101, June 2001 | |
| |
 | @inproceedings{ZWR+01:InterBasedAnalySoftw, ADDRESS = "Snowbird, Utah, USA",
AUTHOR = "D. Ziegenbein and F. Wolf and K. Richter and M. Jersak and R. Ernst",
BOOKTITLE = "Proceedings Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES~'2001)",
MONTH = "jun",
PAGES = "94--101",
TITLE = "Interval-Based Analysis Of Software Processes",
YEAR = "2001",
} | | F. Wolf and R. Ernst, "Execution Cost Interval Refinement in Static Software Analysis," Journal of Systems Architecture, The EUROMICRO Journal, Special Issue on Modern Methods and Tools in Digital System Design, vol. 47, No. 3-4, pp. 339-356, April 2001 | |
| |
| @article{WE01:ExecuCostInterRefin, AUTHOR = "F. Wolf and R. Ernst",
JOURNAL = "Journal of Systems Architecture, The EUROMICRO Journal, Special Issue on Modern Methods and Tools in Digital System Design",
MONTH = "April",
NUMBER = "3-4",
PAGES = "339--356",
TITLE = "Execution Cost Interval Refinement in Static Software Analysis",
VOLUME = "47",
YEAR = "2001",
} | | F. Wolf, J. Kruse, und R. Ernst, "Segment-Wise Timing and Power Measurement in Software Emulation," in Proceedings of the IEEE/ACM Design, Automation and Test in Europe Conference, Designers' Forum, (Munich, Germany), pp. 165-169, March 2001 | |
| |
| @inproceedings{WKE01:SegmeWiseTiminPower, ADDRESS = "Munich, Germany",
AUTHOR = "F. Wolf and J. Kruse and R. Ernst",
BOOKTITLE = "Proceedings of the IEEE/ACM Design, Automation and Test in Europe Conference, Designers' Forum",
MONTH = "mar",
PAGES = "165--169",
TITLE = "Segment-Wise Timing and Power Measurement in Software Emulation",
YEAR = "2001",
} | | F. Wolf, "Intervals in Timing and Power Analysis of Embedded Software," in ACM SIGDA PhDForum at the Design Automation Conference (DAC 2001), (Las Vegas, NV), 2001 | |
| |
| @inproceedings{Wol01:InterTiminPowerAnaly, ADDRESS = "Las Vegas, NV",
AUTHOR = "F. Wolf",
BOOKTITLE = "ACM SIGDA PhDForum at the Design Automation Conference (DAC 2001)",
TITLE = "Intervals in Timing and Power Analysis of Embedded Software",
YEAR = "2001",
} | | F. Wolf and R. Ernst, "Data Flow Based Cache Prediction Using Local Simulation," in Proceedings of the IEEE High Level Design Validation and Test Workshop, (Berkeley, USA), pp. 155-160, November 2000 | |
| |
| @inproceedings{W00:DataFlowBasedCache, ADDRESS = "Berkeley, USA",
AUTHOR = "F. Wolf and R. Ernst",
BOOKTITLE = "Proceedings of the IEEE High Level Design Validation and Test Workshop",
MONTH = "November",
PAGES = "155--160",
TITLE = "Data Flow Based Cache Prediction Using Local Simulation",
YEAR = "2000",
} | | F. Wolf, J. Kruse, und R. Ernst, "Compact Trace Generation and Power Measurement in Software Emulation," in Proceedings of the SPIE International Symposium on Microelectronics and Assembly, (Singapore), pp. 97-108, November 2000 | |
| |
| @inproceedings{WKE00:CompaTraceGenerPower, ADDRESS = "Singapore",
AUTHOR = "F. Wolf and J. Kruse and R. Ernst",
BOOKTITLE = "Proceedings of the SPIE International Symposium on Microelectronics and Assembly",
MONTH = "nov",
PAGES = "97--108",
TITLE = "Compact Trace Generation and Power Measurement in Software Emulation",
YEAR = "2000",
} | | Marek Jersak, Dirk Ziegenbein, Fabian Wolf, Kai Richter, Rolf Ernst, Frank Cieslok, Jürgen Teich, Karsten Strehl, und Lothar Thiele, "Embedded System Design using the SPI Workbench," in Proceedings 3rd International Forum on Design Languages, (Tübingen, Germany), September 2000 | |
| |
| @inproceedings{JZ_Ric_Ern00:EmbedSysteDesigSPI, ADDRESS = "Tübingen, Germany",
AUTHOR = "Marek Jersak and Dirk Ziegenbein and Fabian Wolf and Kai Richter and Rolf Ernst and Frank Cieslok and Jürgen Teich and Karsten Strehl and Lothar Thiele",
BOOKTITLE = "Proceedings 3rd International Forum on Design Languages",
MONTH = "September",
TITLE = "Embedded System Design using the {SPI} Workbench",
YEAR = "2000",
} | | F. Wolf and R. Ernst, "Intervals in Software Execution Cost Analysis," in Proceedings of IEEE/ACM International Symposium on System Synthesis, (Madrid, Spain), pp. 130-135, September 2000 | |
| |
| @inproceedings{WE00:InterSoftwExecuCost, ADDRESS = "Madrid, Spain",
AUTHOR = "F. Wolf and R. Ernst",
BOOKTITLE = "Proceedings of IEEE/ACM International Symposium on System Synthesis",
MONTH = "sep",
PAGES = "130--135",
TITLE = "Intervals in Software Execution Cost Analysis",
YEAR = "2000",
} | | F. Wolf, D. Ziegenbein, und R. Ernst, "Behavioral Intervals in Embedded System Design and Verification," in Tagungsband DFG Workshop Automatisierter Entwurf eingebetteter Systeme, (Karlsruhe, Germany), pp. 71-78, January 2000 | |
| |
| @inproceedings{FDR00:BehavInterEmbedSyste, ADDRESS = "Karlsruhe, Germany",
AUTHOR = "F. Wolf and D. Ziegenbein and R. Ernst",
BOOKTITLE = "Tagungsband DFG Workshop Automatisierter Entwurf eingebetteter Systeme",
MONTH = "jan",
PAGES = "71--78",
TITLE = "Behavioral Intervals in Embedded System Design and Verification",
YEAR = "2000",
} | | F. Wolf and R. Ernst, "Software Timing and Power Estimation of Telecom Systems," Technical University of Braunschweig, Germany, November 1999 | | | |
| @techreport{WE99:STPETelecSyste, ADDRESS = "Germany",
AUTHOR = "F. Wolf and R. Ernst",
INSTITUTION = "Technical University of Braunschweig",
MONTH = "November",
TITLE = "Software Timing and Power Estimation of Telecom Systems",
TYPE = "ESPRIT MEDIA Published Report",
YEAR = "1999",
} | | F. Wolf and R. Ernst, "Software Timing and Power Estimation by Path Clustering," in Proceedings of the ESPRIT/MEDEA Conference on System Level Design, (Antwerpen, Belgium), pp. 81-90, September 1999 | | | | | @inproceedings{WE99:STPEPathCluste, ADDRESS = "Antwerpen, Belgium",
AUTHOR = "F. Wolf and R. Ernst",
BOOKTITLE = "Proceedings of the ESPRIT/MEDEA Conference on System Level Design",
MONTH = "sep",
PAGES = "81--90",
TITLE = "Software Timing and Power Estimation by Path Clustering",
YEAR = "1999",
} | | W. Ye and R. Ernst, "Laufzeitanalyse für eingebettete Programme basierend auf der Programm- und Architekturklassifikation," in Proceedings 5th GI/ITG/GMM Workshop, pp. 17-30, April 1997 | | | |
| @inproceedings{YE97:LaufzEingeProgrBasie, AUTHOR = "W. Ye and R. Ernst",
BOOKTITLE = "Proceedings 5th GI/ITG/GMM Workshop",
MONTH = "April",
PAGES = "17--30",
TITLE = "Laufzeitanalyse für eingebettete Programme basierend auf der Programm- und Architekturklassifikation",
YEAR = "1997",
} | | W. Ye and R. Ernst, "Embedded Program Timing Analysis Based on Path Clustering and Architecture Classification," in Proceedings International Conference on Computer-Aided Design (ICCAD '97), (San Jose, USA), 1997 | | | |
| @inproceedings{YE97:EmbedProgrTiminAnaly, ADDRESS = "San Jose, USA",
AUTHOR = "W. Ye and R. Ernst",
BOOKTITLE = "Proceedings International Conference on Computer-Aided Design (ICCAD~'97)",
TITLE = "Embedded Program Timing Analysis Based on Path Clustering and Architecture Classification",
YEAR = "1997",
} | | W. Ye and R. Ernst, "Worst Case Timing Estimation Based on Symbolic Execution," Institute of Computer Engineering, Technical University of Braunschweig, Germany, October 1995 | | | |
| @techreport{YE95:WorstCaseTiminEstim, AUTHOR = "W. Ye and R. Ernst",
INSTITUTION = "Institute of Computer Engineering, Technical University of Braunschweig, Germany",
MONTH = "October",
TITLE = "Worst Case Timing Estimation Based on Symbolic Execution",
TYPE = "{COBRA} Report '95",
YEAR = "1995",
} | | W. Ye and R. Ernst, "DSP 96002 Processor Simulator," Institute of Computer Engineering, Technical University of Braunschweig, Germany, October 1994 | | | |
| @techreport{YE94:DSP96002ProceSimul, AUTHOR = "W. Ye and R. Ernst",
INSTITUTION = "Institute of Computer Engineering, Technical University of Braunschweig, Germany",
MONTH = "October",
TITLE = "{DSP} 96002 Processor Simulator",
TYPE = "{COBRA} Report '94",
YEAR = "1994",
} | W. Ye, R. Ernst, Th. Benner, und J. Henkel, "Fast Timing Analysis for Hardware-Software Co-Synthesis," in Proceedings IEEE International Conference on Computer Design (ICCD '93), (Cambridge, Massachusetts, USA), pp. 452-457, 1993
IDA-Signatur: K 60/93 | | | | | @inproceedings{YEBH93:FastTiminAnalyHardw, ADDRESS = "Cambridge, Massachusetts, USA",
AUTHOR = "W. Ye and R. Ernst and Th. Benner and J. Henkel",
BOOKTITLE = "Proceedings IEEE International Conference on Computer Design (ICCD~'93)",
PAGES = "452--457",
TITLE = "Fast Timing Analysis for Hardware-Software Co-Synthesis",
YEAR = "1993",
} |
|
|
