Forschung

Ich beschäftige mich mit Multiprozessorarchitekturen und insbesondere mit der Fragestellung der Vorhersagbarkeit großer Chip-Multiprozessoren. Mein Fokus liegt hierbei auf der Verbindungs-Infrastruktur, also dem Network-on-Chip. Dazu arbeite ich in folgenden Projekten:

Lehre

Übungen zu "Advanced Computer Architecture"
Software-Entwicklungs-Praktikum: Videostreaming auf dem Intel Single-Chip Cloud Computer (SCC)
Teamprojekt: Intel 48-Kern Single-Chip Cloud Computer (SCC)
Praktikumsversuch zum Thema Logikanalysator im Praktikum Datentechnik.

Studentische Arbeiten

Folgende Arbeiten sind momentan offen:

Power-Monitoring für eine Many-Core-Plattform (Studienarbeit, Diplomarbeit, Masterarbeit, Bachelorarbeit, Hiwi-Job) [ Kurzbeschreibungen ausblenden ]
In dieser Arbeit soll untersucht werden, welche Auswirkung ein erhöhter Energieverbrauch von einzelnen Programmen auf Programme auf anderen Tiles haben könnte (Überhitzung, Batterielaufzeit, ...). mehr...
Interrupt-Monitoring für eine Many-Core-Plattform (Studienarbeit, Bachelorarbeit, Hiwi-Job) [ Kurzbeschreibungen ausblenden ]
In dieser Arbeit soll zunächst untersucht werden, welche Fehler bei der Interrupt-Generierung auftreten können (Anzahl, Latenz, ...) und wie sich diese auf das Systemverhalten auswirken können. mehr...
Implementation of a Scripted Designflow for Automated SoC Tile Generation (Studienarbeit, Diplomarbeit, Masterarbeit, Bachelorarbeit) [ Kurzbeschreibungen ausblenden ]
Für das RECOMP Projekt soll eine neue MPSoC Architectur entworfen werden. In dieser Architektur sind verschiedene "Tiles" mit einem NoC verbunden. Tiles bestehen aus mehereren Prozessoren, IOs und Speicher. Um den Entwurf zu beschleunigen soll in dieser Arbeit ein Skriptgesteuerter Tilegenerator implementiert werden. mehr...
Benchmarking of a Many-Core System (IDAMC) (Studienarbeit, Bachelorarbeit, Hiwi-Job) [ Kurzbeschreibungen ausblenden ]
Am IDA entsteht derzeit eine Many-Core-Plattform für zuverlässige Echtzeitsysteme. In dieser Arbeit soll die Plattform anhand einiger existierender Benchmarks evaluiert werden. Hierzu sind entsprechende Benchmarks auszuwählen und zu portieren. mehr...
Inter-Core Communication on a Many-Core System (Studienarbeit, Diplomarbeit, Masterarbeit, Bachelorarbeit, Hiwi-Job) [ Kurzbeschreibungen ausblenden ]
Am IDA entsteht derzeit eine Many-Core-Plattform für zuverlässige Echtzeitsysteme. In dieser Arbeit soll ein existierendes Betriebssystem (FreeRTOS) auf die Plattform portiert werden und hierauf Möglichkeiten zur Inter-Core Kommunikation implementiert werden. mehr...

Publikationen (Konferenzen / Journals)

Das aufgeführte Material ist urheberrechtlich geschützt. Das entsprechende Urheberrecht ist zu beachten.

Jonas Diemer, Daniel Thiele und Rolf Ernst, "Formal Worst-Case Timing Analysis of Ethernet Topologies with Strict-Priority and AVB Switching" in 7th IEEE International Symposium on Industrial Embedded Systems (SIES12), Juni 2012. Invited Paper, to appear.
X @Inproceedings{diemer2012formal, AUTHOR = "Jonas Diemer and Daniel Thiele and Rolf Ernst", BOOKTITLE = "7th IEEE International Symposium on Industrial Embedded Systems (SIES12) ", MONTH = "6", NOTE = "Invited Paper, to appear", TITLE = "Formal Worst-Case Timing Analysis of Ethernet Topologies with Strict-Priority and AVB Switching", YEAR = "2012", }
Rodney Cummings, Kai Richter, Rolf Ernst, Jonas Diemer und Arkadeb Ghosal, "Exploring Use of Ethernet for In-Vehicle Control Applications: AFDX, TTEthernet, EtherCAT, and AVB" in SAE 2012 World Congress & Exhibition, April 2012. SAE Technical Paper 2012-01-0196.
X @Inproceedings{cummings2012exploring, AUTHOR = "Rodney Cummings and Kai Richter and Rolf Ernst and Jonas Diemer and Arkadeb Ghosal", BOOKTITLE = "SAE 2012 World Congress \& Exhibition", MONTH = "4", NOTE = "SAE Technical Paper 2012-01-0196", TITLE = "Exploring Use of Ethernet for In-Vehicle Control Applications: AFDX, TTEthernet, EtherCAT, and AVB", URL = "http://papers.sae.org/2012-01-0196", YEAR = "2012", }
Jonas Diemer, Jonas Rox und Rolf Ernst, "Modeling of Ethernet AVB Networks for Worst-Case Timing Analysis" in MATHMOD 2012 - 7th Vienna International Conference on Mathematical Modelling, (Vienna, Austria), Februar 2012 [ IDA-Link]
X @Inproceedings{diemer2012modeling, ADDRESS = "Vienna, Austria", AUTHOR = "Jonas Diemer and Jonas Rox and Rolf Ernst", BOOKTITLE = "MATHMOD 2012 - 7th Vienna International Conference on Mathematical Modelling", MONTH = "2", TITLE = "Modeling of Ethernet AVB Networks for Worst-Case Timing Analysis", YEAR = "2012", }
Philip Axer, Jonas Diemer, Mircea Negrean, Maurice Sebastian, Simon Schliecker und Rolf Ernst, "Mastering MPSoCs for Mixed-Critical Applications" IPSJ Transactions on System LSI Design Methodology, vol. 4, August 2011
X @Article{ADN+11:MasteMPSoCMixedAppli, AUTHOR = "Philip Axer and Jonas Diemer and Mircea Negrean and Maurice Sebastian and Simon Schliecker and Rolf Ernst", JOURNAL = "IPSJ Transactions on System LSI Design Methodology", MONTH = "August", TITLE = "Mastering MPSoCs for Mixed-Critical Applications", VOLUME = "4", YEAR = "2011", }
Jonas Diemer, Jonas Rox, Mircea Negrean, Steffen Stein und Rolf Ernst, "Real-Time Communication Analysis for Networks with Two-Stage Arbitration" in Proceedings of the ninth ACM International Conference on Embedded Software (EMSOFT), (Taipei, Taiwan), pp. 243-252, ACM, Oktober 2011. ISBN 978-1-4503-0714-7.
X @Inproceedings{diemer2011realtime, ADDRESS = "Taipei, Taiwan", AUTHOR = "Jonas Diemer and Jonas Rox and Mircea Negrean and Steffen Stein and Rolf Ernst", BOOKTITLE = "Proceedings of the ninth ACM International Conference on Embedded Software (EMSOFT)", MONTH = "Oct", NOTE = "ISBN 978-1-4503-0714-7", PAGES = "243--252", PUBLISHER = "ACM", SERIES = "EMSOFT \\\'11", TITLE = "Real-Time Communication Analysis for Networks with Two-Stage Arbitration", URL = "http://doi.acm.org/10.1145/2038642.2038680", YEAR = "2011", }
Steffen Stein, Matthias Ivers, Jonas Diemer und Rolf Ernst, "A polynomial time algorithm for computing response time bounds in static priority scheduling with convex event models" in Euromicro Conference on Real-Time Systems (ECRTS'10), Juli 2010
X @Inproceedings{Ste10:polynalgorcompurespo, AUTHOR = "Steffen Stein and Matthias Ivers and Jonas Diemer and Rolf Ernst", BOOKTITLE = "Euromicro Conference on Real-Time Systems (ECRTS\'10)", MONTH = "July", TITLE = "A polynomial time algorithm for computing response time bounds in static priority scheduling with convex event models", YEAR = "2010", }
Jonas Diemer und Rolf Ernst, "Back Suction: Service Guarantees for Latency-Sensitive On-Chip Networks" in Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'10), Mai 2010
X @Inproceedings{DE10:SuctiServiGuaraLaten, AUTHOR = "Jonas Diemer and Rolf Ernst", BOOKTITLE = "Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS\'10)", MONTH = "May", TITLE = "{Back Suction: Service Guarantees for Latency-Sensitive On-Chip Networks}", YEAR = "2010", }
Jonas Diemer, Rolf Ernst und Michael Kauschke, "Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip" in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 2010), Januar 2010 [ IDA-Link]
X @Inproceedings{DEK10:EfficThrouLatenNetwo, AUTHOR = "Jonas Diemer and Rolf Ernst and Michael Kauschke", BOOKTITLE = "Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 2010)", MONTH = "January", TITLE = "Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip", YEAR = "2010", }
Jonas Diemer und Rolf Ernst, "A Link Arbitration Scheme for Quality of Service in a Latency-Optimized Network-on-Chip" in Proceedings of the conference on Design, Automation and Test in Europe (DATE), April 2009 [ IDA-Link]
X @Inproceedings{Die09:ArbitSchemQualiServi, AUTHOR = "Jonas Diemer and Rolf Ernst", BOOKTITLE = "Proceedings of the conference on Design, Automation and Test in Europe (DATE)", MONTH = "April", TITLE = "A Link Arbitration Scheme for Quality of Service in a Latency-Optimized Network-on-Chip", YEAR = "2009", }

Sonstige Publikationen

Das aufgeführte Material ist urheberrechtlich geschützt. Das entsprechende Urheberrecht ist zu beachten.

Rolf Ernst, Glenn Farrall, Jonas Diemer, Henrik Theiling, Matthieu Lemerre, Swapnil Gandhi und Madeleine Faugère, "TUTORIAL: Multi-Core Platforms for Mixed-Critical Embedded Systems." März 2012. Tutorial..
X @Misc{ernst2012tutorial, AUTHOR = "Rolf Ernst and Glenn Farrall and Jonas Diemer and Henrik Theiling and Matthieu Lemerre and Swapnil Gandhi and Madeleine Faugère", HOWPUBLISHED = "Tutorial", MONTH = "3", TITLE = "TUTORIAL: Multi-Core Platforms for Mixed-Critical Embedded Systems", URL = "http://www.date-conference.com/conference/session/D1", YEAR = "2012", }
Jonas Rox, Jonas Diemer und Rolf Ernst, "Formal Timing Analysis of Ethernet AVB for Industrial Automation." Januar 2012. Presentation at 802.1Qav Interim Meeting, Munich, Jan 16-20, 2012..
X @Misc{rox2012formal1, AUTHOR = "Jonas Rox and Jonas Diemer and Rolf Ernst", HOWPUBLISHED = "Presentation at 802.1Qav Interim Meeting, Munich, Jan 16-20, 2012", MONTH = "1", TITLE = "Formal Timing Analysis of Ethernet AVB for Industrial Automation", URL = "http://www.ieee802.org/1/files/public/docs2012/new-avb-rox-formal-timing-analysis-0112.pdf", YEAR = "2012", }
Jonas Diemer, "Timing Analysis of Ethernet AVB for Real-Time Systems." Oktober 2011. Presentation at the 5th Symtavision NewsConference
X @Unpublished{systems2011jonas, AUTHOR = "Jonas Diemer", MONTH = "Oct", NOTE = "Presentation at the 5th Symtavision NewsConference", TITLE = "Timing Analysis of Ethernet AVB for Real-Time Systems", URL = "http://www.symtavision.com/newsconference2011.html", YEAR = "2011", }
Jonas Diemer und Rolf Ernst, "Achieving Predictability in General-Purpose Many-Cores." September 2010. Abstract for Intel® European Research & Innovation Conference
X @Unpublished{Die10:AchiePrediGenerManyC, AUTHOR = "Jonas Diemer and Rolf Ernst", MONTH = "September", NOTE = "Abstract for Intel\textregistered European Research \& Innovation Conference", TITLE = "Achieving Predictability in General-Purpose Many-Cores", YEAR = "2010", }
Jonas Diemer und Rolf Ernst, "Predictability in General-Purpose Many-Cores." September 2010. Poster, Intel® European Research & Innovation Conference.
X @Misc{Die10:PrediinGenerManyC, AUTHOR = "Jonas Diemer and Rolf Ernst", HOWPUBLISHED = "Poster", MONTH = "September", NOTE = "Intel\textregistered European Research \& Innovation Conference", TITLE = "Predictability in General-Purpose Many-Cores", YEAR = "2010", }
Jonas Diemer und Rolf Ernst, "Challenges of Mapping Real-Time Streaming Applications to General Purpose Manycores." Juni 2010. Map2MPSoC Workshop 2010, Rheinfels 2010 [ IDA-Link]
X @Unpublished{Die10:ChallMappiRealTStrea, AUTHOR = "Jonas Diemer and Rolf Ernst", MONTH = "June", NOTE = "Map2MPSoC Workshop 2010, Rheinfels 2010", TITLE = "Challenges of Mapping Real-Time Streaming Applications to General Purpose Manycores", YEAR = "2010", }
Rolf Ernst und Jonas Diemer, "Mehrprozessor-Computersystem." April 2009. Patentschrift, DE 10 2009 016 742 B4.
X @Misc{EX09:Mehrp, AUTHOR = "Rolf Ernst and Jonas Diemer", HOWPUBLISHED = "Patentschrift", MONTH = "April", NOTE = "DE 10 2009 016 742 B4", TITLE = "Mehrprozessor-Computersystem", URL = "http://depatisnet.dpma.de/DepatisNet/depatisnet?action=bibdat\&docid=DE102009016742B4", YEAR = "2009", }
Steffen Stein, Jonas Diemer, Matthias Ivers, Simon Schliecker und Rolf Ernst, "On the Convergence of the SymTA/S analysis" TU Braunschweig, Braunschweig, Germany, November 2008 [ IDA-Link]
X @Techreport{SE08:theConvetheSymTAanaly, ADDRESS = "Braunschweig, Germany", AUTHOR = "Steffen Stein and Jonas Diemer and Matthias Ivers and Simon Schliecker and Rolf Ernst", INSTITUTION = "TU Braunschweig", MONTH = "nov", TITLE = "On the Convergence of the SymTA/S analysis", YEAR = "2008", }
Jonas Diemer, "A SystemC Simulation Environment for On-Chip Traffic Control Strategies for Chip-Multiprocessors" Diplomarbeit, Technische Universität Braunschweig, Mai 2007 IDA-Signatur: DPA 3424 [ IDA-Link]
X @Mastersthesis{Die07:SysteSimulEnvirOnChi, AUTHOR = "Jonas Diemer", MONTH = "May", SCHOOL = "Technische Universit{\"a}t Braunschweig", TITLE = "A SystemC Simulation Environment for On-Chip Traffic Control Strategies for Chip-Multiprocessors", CONTENTTYPE = "Diplomarbeit", YEAR = "2007", }
Jonas Diemer, "Realization of a Spectral Analysis Capability in an Embedded System" Studienarbeit, Technische Universität Braunschweig, 2006 IDA-Signatur: STA 3358 [ IDA-Link]
X @Mastersthesis{Die06:RealiSpectAnalyCapab, AUTHOR = "Jonas Diemer", SCHOOL = "Technische Universit{\"a}t Braunschweig", TITLE = "Realization of a Spectral Analysis Capability in an Embedded System", CONTENTTYPE = "Studienarbeit", YEAR = "2006", }

Instituts-Anschrift:

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Fax: (0531) 391-4587

sekretariat(at)ida.ing.tu-bs.de

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