IDA is the Lead Institution for Low Power Digital Design in the Cadence Academic Network.
For a complete list of all network members please check out the official Cadence-Website.
We are relying on Cadence Tools in following classes:
VLSI Design I conveys the theoretical background of VLSI. It offers an introduction to digital integrated circuits design, CMOS devices and manufacturing technology. Students learn about sequential and combinational circuits, as well as test and verification strategies. (link to lecture)
The Lab VLSI Design I aims for the understanding of modern standard-cell synthesis flows. Students implement a micro-controller in VHDL, develop appropriate testbenches and synthesize the design down to place & route. In the course of the lab students learn how to use Cadence RTL Compiler, Incisive Unified Simulator and SoC Encounter. (link to lecture)
Processor Layout from Lab
VLSI Design II teaches the concepts of system design. The lecture covers components of modern embedded systems such as: memories, controllers, bus architectures. Moreover, the students receive an introduction in System on Chip (SoC) and Electronic System Level Design (ESL). (link to lecture)
The Lab VLSI Design II is dedicated to Electronic System Level Design. The students develop a JPEG compressor in form of a virtual platform. The system contains an ARM9 subsystem, an OCP system bus, multiple input/output peripherals and a dedicated DCT accelerator, which has to developed in the scope of the lab. The lab heavily relies on the Cadence Incisive Unified Simulator for RTL / SystemC co-simulation (link to lab).
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flatflow_demo
hierflow_demo
lpflow_demo
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Home VLSI Systems Group
Prof. Dr. Ing. Mladen Berekovic
Resp. Engineer: Thomas Schuster
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