Literatur

Wichtige Beiträge zum Download:

• Kapitel 1: Übersicht zu eingebetteten Systemen
  • R. Ernst, Automatisierter Entwurf eingebetteter Systeme, at - Automatisierungstechnik, p. 285-294, July 1999.
  • R. Ernst, Codesign of Embedded Systems: Status and Trends, IEEE Journal Design & Test of Computers, p. 45-54, April 1998.
    PDF (104 KB)
  
  
• Kapitel 2: Systemspezifikation und abstrakte Modellierung
• D. Harel, STATECHARTS: A Visual Formalism for Complex Systems, Science of Computer Programming, No. 8, p. 231-274, North-Holland, 1987.
  PDF (1853 KB)
• D. Harel and A. Naamad, The STATEMATE Semantics of Statecharts, ACM Transactions on Software Engineering and Methodology, Vol.5, No.4, p. 293-333, 1996.
  PDF (338 KB)
• A. S. Tanenbaum, Moderne Betriebssysteme, 2. Auflage, Studienbücher der Informatik, s. 42-73, Hanser Verlag, 1995.
  PDF (2836 KB)
• E. A. Lee, D. G. Messerschmitt, Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing, IEEE Transactions on Computers, Vol. C-36, No. 1, p. 24-35, January 1987.
  PDF (2155 KB)
• E. A. Lee, D. G. Messerschmitt, Synchronous Data Flow, Procedings of the IEEE, Vol. 75, No. 9, p. 1235-1245, September 1987.
  PDF (1943 KB)
• S. D. Stearns, Digitale Verarbeitung analoger Signale, s. 170-173, R.Oldenbourg Verlag, 1979.
  PDF (283 KB)
• VSI Alliance™ System-Level Design Development Working Group. Model Taxonomy. Version 2.1, July 2001
  PDF (255 KB)
• G. Kahn, The Semantics of a Simple Language for Parallel Programming, Information Processing '74: Proceedings of the IFIP Congress, p. 471-475, North-Holland, 1974.
  PDF (704 KB)


• Kapitel 3: Zielarchitekturen
• R. Ernst, Hardware-Software Co-Design, chapter Target Architectures, p. 113-148, Kluwer Academic Publishers, 1997.
  PDF (3432 KB)
• R. Ernst, Embedded System Architectures, A. A. Jerraya and J. Mermet (eds.), System-Level Synthesis, p. 1-43, Kluwer Academic Publishers, 1999.
  PDF (448 KB)
• M. Zeller, Von ARM und SOC, c't, Heft 2, s. 203, 2002.
  PDF (650 KB)
• Sarah Ewen, Console Yourself, SCEE Technology Group, SONY
  PDF (703 KB)
• James Russell, Introduction to PlayStation(R)2 Architecture, SCEE Technology Group, SONY
  PDF (299 KB)
• Paul Holman, The Technology behind PlayStation(R)2, SCEE Technology Group, SONY
  PDF (812 KB)
• C. L. Liu, J. W. Layland, Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment, Journal of the Association for Computing Machinery, Vol. 20, No. 1, p. 46-61, January 1973.
  PDF (954 KB)
• K. W. Tindell, An Extendible Approach for Analysing Fixed Priority Hard Real-Time Tasks, YCS 189, Department of Computer Science, University of York, 1992.
  PDF (180 KB),
• L. Sha, S. S. Sathaye, Distributed System Design Using Generalized Rate Monotonic Theory, Technical Report, Software Engineering Institute, Carnegie Mellon University, September, 1995.
  PDF (111 KB),

Handbücher, Anwendungsbeispiele, etc
• DSP56000 - 24-bit Digital Signal Processor Family Manual, Motorola, Inc., 1995.
  PDF (2111 KB)
• MCS(R) 51 Microcontroller Family User's Manual, Intel, 1994.
  PDF (15MB)
• C500 - Architecture and Instruction Set, User's Manual, Infineon Technologies AG, July 2000.
  PDF (970 KB)
• Generating Sinusoidal 3-Phase-Currents for Induction Machines with a Time-Optimized Algorithm for the C504/C508 Capture Compare Unit, Application Note, Infineon Technologies AG, 1999.
  PDF (635 KB)
• MPC555, User's Manual, Motorola, Inc., March 1999.
  Section 1 (Overview) (58 KB), Section 17 (TPU 3) (363 KB)
• SH-DSP Microprocessor, Overview, Hitachi Micro Systems, Inc., November, 1996.
  PDF (177 KB)
• PowerNP NP4GX Network Processor, IBM Corporation, 2000.
  PDF (289 KB)
• IBM PowerNP NP4GS3 Network Processor, User's Manual, IBM Corporation, February 2002.
  PDF (8884 KB)
• Vector Unit Architecture for Emotion Synthesis, IEEE Micro, March-April, p. 40-47, 2000.
  PDF (129 KB)


• Kapitel 4: Entwurf
• S. Liao, S. Devadas, K. Keutzer, S. Tjiang, A. Wang, Storage Assignment to Decrease Code Size, ACM Transactions on Programming Languages and Systems, Vol. 18, No. 3, p. 235-253, May 1996.
  PDF (141 KB),
• P. Chou, G. Borriello, Software scheduling in the co-synthesis of reactive real-time systems, Proceedings of the 31st ACM/IEEE Design Automation Conference, p. 1-4, San Diego, California, United States, 1994.
  PDF (179 KB),

Weiterführende Literatur:

• Kap 2: Systemspezifikation und abstrakte Modellierung
• Axel Jantsch. Modeling Embedded Systems and SoCs. Morgan Kaufman Publishers, 2004.
• B. Bailey, G. Martin, Th. Anderson. Taxonomies for the Development and Verification of Digital Systems. Springer 2005.

VHDL
• Peter J. Ashenden, The Designer's Guide to VHDL, 2nd Edition, Morgan Kaufmann Publishers, 2001.
• Peter J. Ashenden, The Student's Guide to VHDL, Morgan Kaufmann Publishers, 1998.
• VHDL Online
• Jayaram Bhasker, A Guide to VHDL Syntax, Prentice-Hall, 1995.

Spezifikation, Methodik
• Daniel D. Gajski, F. Vahid, S. Narayan, J. Gong, Specification and Design of Embedded Systems, Prentice-Hall, 1994.
• Connie U. Smith, Performance Engineering of Software Systems, Addison-Wesley Publishing Company, 1990.
• Jean Paul Calvez, Embedded Real-Time Systems, John Wiley & Sons, Chichester, England, 1993.
• A. Benveniste, G. Berry, The Synchronous Approach to Reactive and Real-Time Systems, Proceedings of the IEEE, Vol. 79, No. 9, 1991, p. 1270-1282.
• N. Halbwachs, Synchronous Programming of Reactive Systems, Kluwer Academic Publishers, 1993.

Automatentheorie
• J. Hartmanis, S. D. Stearns, Algebraic Structure Theory of Sequential Machines, Prentice-Hall, 1965.

Petri-Netze
• Wolfgang Reisig, Petrinetze - Eine Einführung, Studienreihe Informatik, 2. Auflage, Springer, 1986.
• J. L. Peterson, Petri Net Theory and the Modeling of Systems, Prentice-Hall, 1981.
• Peter H. Starke, Analyse von Petri-Netz-Modellen, Teubner Stuttgart, 1990.

Digitale Signalverarbeitung
• Maurice Bellanger, Digital Processing of Signals - Theory and Practice, 2nd Edition, Wiley, Teubner, 1989.
• Lawrence R. Rabiner, Bernhard Gold, Theory and Application of Digital Signal Processing, Prentice-Hall, 1975.
• A. Oppenheim, R. Schafer, Digital Signal Processing, Prentice-Hall, 1975.
• Samuel D. Stearns, Don R. Hush, Digitale Verarbeitung analoger Signale, 6. Auflage, Oldenbourg, München, 1994.

• Kap 3: Zielarchitekturen

Zielarchitektur
• Helmut Bähring, Mikrorechner-Systeme, Mikroprozessoren, Speicher, Peripherie, Springer-Verlag, 1991.
• Mikrocontrollers, Siemens Data Book, 1994/1995.
• M68300 Family / TPU - Time Processor Unit, Reference Manual, Motorola, 1990.
• Hcll MC68HCllK4 - Technical Data, Motorola, 1992.
• ADSP-2106x SHARC User's Manual, 1. Auflage, Analog Devices, 1995.

Betriebssysteme
• Andrew S. Tanenbaum, Operating Systems - Design and Implementation, Prentice-Hall, 1987.

Rate Monotonic Scheduling (RMS)
• C. Liu, J. Layland, Scheduling Algorithm for Multiprogramming in a Hard-Real-Time Environment, Journal of the ACM, Vol. 20, p. 46-61, 1973.
• L. Sha, R. Rajkumar, S. S. Sathaye, Generalized Rate-Monotonic Scheduling Theory: A Framework for Developing Real-Time Systems, IEEE Proceedings, Vol. 82, No. 1, January 1994.

Deadline Monotonic Scheduling (DMS)
• J. Y. Leung, J. Whitehead, On the Complexity of Fixed-Priority Scheduling of Periodic Real-Time Tasks, Performance Evaluation, Vol. 2, No. 4, p. 237-250, December 1982.

Prozeß-Synchronisation
• L. Sha, R. Rajkumar, J. P. Lehoczky, Priority Inheritance Protocols: An Approach to Real-Time Synchronization, IEEE Transactions on Computers, Vol. 39, No. 9, September 1990.
• Edward A. Lee, David G. Messerschmitt, Synchronous Data Flow, Proceedings of the IEEE, Vol. 75, No. 9, September 1987.

Statisches Scheduling
• P. Chou, G. Borriello, Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems, 31st Design Automation Conference, San Diego, CA, June 1994.
• J. Xu, D. L. Parnas, On Satisfying Timing Constraints in Hard-Real-Time Systems, IEEE Transactions on Software Engineering, Vol. 19, No. 1, January 1993.

Reconfigurable Computing
• K. Compton and S. Hauck, Reconfigurable Computing: A Survey of Systems and Software, ACM Computing Surveys, Vol. 34, No. 2, pp. 171-210, , June 2002.
  PDF
• A. do Carmo Lucas, S. Heithecker and R. Ernst, XCell: A reconfigurable platform for high-end real-time digital film processing.
  PDF

Low Power
• V. Venkatachalam and M. Franz, Power Reduction Techniques For Microprocessor Systems, ACM Computing Surveys, Vol. 37, No. 3, pp. 195-237., September 2005.
  PDF
• R. Kakerow, Low Power Design Methodologies for Mobile Communication, Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Freiburg, Germany, September 2002.
  PDF

• Kap 4: Entwurf

Embedded System Design
• Wayne Wolf, Computers as Components: Principles of Embedded System Design, Morgan Kaufman Publishers, revised edition
• Peter Marwedel, Embedded System Design, Springer

Synthese
• Petra Michel (Hrsg.) et al., The Synthesis Approach to Digital System Design, Kluwer Academic Publishers, 1992.
• Daniel D. Gajski et al., High-Level Synthesis - Introduction to Chip and System Design, Kluwer Academic Publishers, 1992.
• G. De Micheli (Hrsg.) et al., Design Systems for VLSI Circuits - Logic Synthesis and Silicon Compilation, Martinus Nijhoff Publishers, Dordrecht, 1987.
• G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.
• Tsutomu Sasao (Hrsg.), Logic Synthesis and Optimization, Kluwer Academic Publishers, Boston, 1993.
• Catherine H. Gebotys, Mohamed I. Elmasry, Optimal VLSI Architectural Synthesis - Area, Performance and Testability, Kluwer Academic Publishers, 1992.
• Daniel D. Gajski (Hrsg.), Silicon Compilation, Addison-Wesley Publishing Company, Reading, Massachusetts, 1988.
• Robert K. Brayton et al., Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984.
• Raul Camposano, Wayne Wolf (Hrsg.), High-Level VLSI Synthesis, Kluwer Academic Publishers, 1991.
• E.S. Kuh, T. Ohtsuki, Recent Advances in VLSI Layout, Proceedings of the IEEE, Vol. 78, No. 2, February 1990.
• M.C. McFarland et al., The High-Level Synthesis of Digital Systems, Proceedings of the IEEE, Vol. 78, No. 2, February 1990
• B. Eschermann, Funktionaler Entwurf digitaler Schaltungen, Springer-Verlag, 1993

Compiler
• A. V. Aho, S.C. Johnson, Optimal Code Generation for Expression Trees, Journal of the ACM, Vol. 23, No. 3, p. 488-501, 1976.
• A. V. Aho, R. Sethi, J. D. Ullmann, Compilers: Principles, Techniques and Tools, Addison-Wesley Publishing, 1986.
• U. Banerjee, Loop Parallelization, Kluwer Academic Publishers, 1994
• G. J. Chaitin, Register Allocation and Spilling Via Graph Coloring, ACM SIGPLAN Notices, Vol. 17, no. 6, p. 201-207, 1982.
• J. L. Hennessy, D. A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, 1990.
• P. Marwedel, G. Goossens (Hrsg.), Code Generation for Embedded Processors, Kluwer Academic Publishers, 1995.

Optimierung
• K. Mehlhorn, Graph Algorithms and NP-Completeness, Springer-Verlag, Berlin, 1984.
• C. H. Papadimitriou, K. Steiglitz, Combinatorial Optimization - Algorithms and Complexity, Prentice-Hall, 1982.
• R. Sedgewick, Algorithms, Addison-Wesley Publishing Company, 1988.
• M. M. Syslo, N. Deo, J. S. Kowalik, Discrete Optimization Algorithms - with Pascal Programs, Prentice-Hall, 1983.