Intensive block lecture: Introduction to Digital Hardware Design ET-IDA-028

This laboratory-lecture would be held in sumer semester in English language and offered as a block laboratory to interested students.

Time and place would be agreed on with the interested students.
number of places is limited to a maximum of 10 students.

Interested students are kindly asked to send an e-mail to:
M. Ayoob Basil TU <m.ayoob@tu-braunschweig.de>

IMPORTANT NOTICE: to all participating students

To save time, it is highly advised to download the Xilinx ISE software on your laptops prior to the lab from the following site: 
http://www.xilinx.com/support/download/index.htm 

Please also download to your own laptop the Digilent ADEPT software which is needed to download FPGA bitstreams onto the the boards: 
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2  

Lecture time : start 9:00
Place: Room 1111, 11th floor, Hans-Sommer Str. 66, 38106 Braunschweig

Lecture material would be available here: Lecture Material 

Lecture description: 

 Duration: about 28 hours, over 5 full days in addition to some training hours.
 Lecture contents: (Contents)

Requirements

1- Basic knowledge in digital circuits principles
2- Preferred to bring own laptop. Design software would be offered free.
3. A design board would be given by instructors.

Expected credit-points is 4. To be countable, You have to get the approval of your own department. For CSE master student no need for approval.

Interested students are kindly asked to contact Prof. Adi or send an e-mail to 

Aims
At the end of this course, attendees will be able to develop synchronous digital circuits from high level functional specifications and prototype them on to FPGA hardware using a standard hardware description language (Verilog).

Objectives

1. To explain and illustrate combinatorial and sequential circuits and present a number of ways of designing, and capturing them in a standard hardware description language;
2. To explain and illustrate basic and linked state machines for controlling circuit behaviour, and present a number of ways of designing, and capturing them in standard hardware description language;
3. To explain and illustrate the notion of modular design and design for reuse, and ways of capturing this in a standard hardware description language;
4. To present a digital circuit development flow that captures functional specification, design, simulation, synthesis, implementation and testing on FPGA hardware, and illustrate it using a commercial tool suite.

Contents
All lectures blocks are linked to Verilog design language and accompanied with hardware design samples on Xilinx hardware FPGA design kit.

-          Introduction to digital circuits, combinational digital hardware

-          synchronous digital hardware, coding styles, state machines

-          Data display VGA standard

-          Sample project “Snake Game”

 Lecture contents: (Contents)

Text Book:

Digital Design (Verilog) 
An Embedded Systems Approach Using Verilog 
By Peter J. Ashenden 
Copyright 2008, Morgan Kaufmann Title, ISBN: 978-0-12-369527-7 
 

 Lecture Material