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Fault Tolerance

 

Fault-tolerant design and testing of devices


Fault tolerance in ASICs and FPGAs

  • high-performance on-chip processor system in fault-tolerant design for automotive and space applications
  • Dynamic Partial Reconfiguration (DPR) and Soft Error Mitigation (SEM) for FPGAs


Radiation characterisation of devices

  • in-situ testing of memory devices and FPGAs
  • real time event detection and recording
  • flexible and easy adaptable platform

 

 

Address:
Hans-Sommer-Street 66
38106 Braunschweig
Fon: +49 (0)531 391-3734
Fax: +49 (0)531 391-4587

Office hours:
Mon: 
10:15-11:30
and 14:00-15:00
Tue: 
10:15-11:30
and 14:00-15:00
Wed: 
14:00-15:00
Thu: 
10:15-11:30
and 14:00-15:00
Fri: 
10:15-11:30
and 14:00-15:00
sekretariat(at)ida.ing.tu-bs.de

Address of Prof. Jukan's workgroup:

Hans-Sommer-Street 66
38106 Braunschweig

Fon: +49 (0)531 391-5286
Fax: +49 (0)531 391-5296