Alexander Dörflinger
 
Raum: 1307
Telefon: +49 531 391 9680
Telefax: +49 531 391 4587
E-Mail:
 
Institut für Datentechnik und Kommunikationsnetze
Hans-Sommer-Straße 66
38106 Braunschweig

Forschung

  • Controlling Concurrent Change (http://ccc-project.org):
    • Subproject B3: Safety and Availability
    • Subproject C1: Aerospace Electronics
  • Data Processing Units (DPUs) for spacecrafts

Lehre

Publikationen

Das aufgeführte Material ist urheberrechtlich geschützt. Das entsprechende Urheberrecht ist zu beachten.

Björn Fiethe, Alexander Dörflinger und Harald Michalik, "Efficient Image Data Processing for the JANUS Instrument on JUICE" in Eurospace DASIA 2019, 2019, (to appear).BibTeX Code anzeigen: Efficient Image Data Processing for the JANUS Instrument on JUICE    
Alexander Dörflinger, Mark Albers, Björn Fiethe, Harald Michalik, Mischa Möstl, Johannes Schlatow und Rolf Ernst, "Demonstrating Controlled Change for Autonomous Space Vehicles" in NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2019. BibTeX Code anzeigen: Demonstrating Controlled Change for Autonomous Space Vehicles    
Mischa Möstl, Alexander Dörflinger, Mark Albers, Harald Michalik und Rolf Ernst, "Self-Adaptation for Availability in CPU-FPGA Systems under Soft Errors" in NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2019. BibTeX Code anzeigen: Self-Adaptation for Availability in CPU-FPGA Systems under Soft Errors    
Alexander Dörflinger, Mark Albers, Johannes Schlatow, Björn Fiethe, Harald Michalik, Phillip Keldenich und Sándor P. Fekete, "Hardware and Software Task Scheduling for ARM-FPGA Platforms" in NASA/ESA Conference on Adaptive Hardware and Systems (AHS), (Edinburgh, UK), August 2018. BibTeX Code anzeigen: Hardware and Software Task Scheduling for ARM-FPGA Platforms    
Alexander Dörflinger, Mark Albers, Björn Fiethe und Harald Michalik, "Hardware Acceleration in Genode OS Using Dynamic Partial Reconfiguration" in Architecture of Computing Systems -- ARCS, 2018. BibTeX Code anzeigen: Hardware Acceleration in Genode OS Using Dynamic Partial Reconfiguration    
A. Dörflinger, B. Fiethe, H. Michalik, S. P. Fekete, P. Keldenich und C. Scheffer, "Resource-efficient dynamic partial reconfiguration on FPGAs for space instruments" in NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2017. BibTeX Code anzeigen: Resource-efficient dynamic partial reconfiguration on FPGAs for space instruments    
H. Michel, H. Guzmán-Miranda, A. Dörflinger, H. Michalik und M. A. Echanove, "SEU fault classification by fault injection for an FPGA in the space instrument SOPHI" in NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2017. BibTeX Code anzeigen: SEU fault classification by fault injection for an FPGA in the space instrument SOPHI    
Instituts-Anschrift:
Hans-Sommer-Straße 66
38106 Braunschweig

Fon: (0531) 391-3734
Fax: (0531) 391-4587
sekretariat(at)ida.ing.tu-bs.de

Anschrift AG Prof. Jukan:

Hans-Sommer-Straße 66
38106 Braunschweig

Fon: (0531) 391-5286
Fax: (0531) 391-5296