Future computer architectures are likely to have tens to hundreds of processor cores, running different application classes in parallel. There will be “classical” independent processes, tightly coupled parallel applications and stream applications, all of which have different service requirements. These applications compete for shared ressources such as on-chip memories and communication infrastructure.
In this project, we look at techniques to combine these heterogeneous requirements and make such architectures predictable. Examples are partitioning of on-chip memories, quality of service for the network-on-chip, and mechanisms for flexible yet efficient data transfers, just to name a few.
The listed material is protected by copyright. The corresponding copyright must be observed.
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Jonas Diemer, Rolf Ernst and Michael Kauschke, "Efficient Throughput-Guarantees for Latency-Sensitive Networks-On-Chip" in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 2010), Januar 2010. |
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@inproceedings{DEK10:EfficThrouLatenNetwo, author = {Jonas Diemer and Rolf Ernst and Michael Kauschke}, |
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Jonas Diemer and Rolf Ernst, "Back Suction: Service Guarantees for Latency-Sensitive On-Chip Networks" in Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'10), Mai 2010. |
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@inproceedings{DE10:SuctiServiGuaraLaten, author = {Jonas Diemer and Rolf Ernst}, |
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Rolf Ernst and Jonas Diemer, "Mehrprozessor-Computersystem", April 2009. Patentschrift, DE 10 2009 016 742 B4. |
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@misc{EX09:Mehrp, author = {Rolf Ernst and Jonas Diemer}, |
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Jonas Diemer and Rolf Ernst, "A Link Arbitration Scheme for Quality of Service in a Latency-Optimized Network-on-Chip" in Proceedings of the conference on Design, Automation and Test in Europe (DATE), April 2009. |
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@inproceedings{Die09:ArbitSchemQualiServi, author = {Jonas Diemer and Rolf Ernst}, |
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