Efficient routing techniques in heterogeneous 3D Networks-on-Chip

Over the past four decades, chip integration capacity has been continually following Moore’s law. To fully utilize the integration capacity in the billion-transistor era, NoCs have received significant attention over the past 10 years due to good scalability. However, scaling on-chip networks over two dimensions to accommodate tens or hundreds of cores are not efficient as increasing the number of cores over a 2D plane soon introduces communication bottleneck due to long interconnects and distance.

Under such circumstances, 3D integration technologies emerge, such as Through-Silicon-Vias (TSVs), thinned silicon and silicon-to-silicon fine-pitch interconnections, wireless communication between 2D planes and 3D wafer wire-bonding technology. These technologies enable to stack multiple dies on a single chip, creating 3D Integrated Circuits (3D-ICs) and offering an opportunity to be the next performance growth engine. 3D-ICs may enable heterogeneous and new classes of complex applications with significantly improved performance, energy efficiency, product miniaturization, cost reduction, and modular design for improved time to market. Such technologies are currently available from a number of companies and labs such as IBM, IMEC, Honda, Tezzaron Semiconductor Corporation and MIT Lincoln Laboratory.

In this topic, the student’s task is to investigate the most promising 3D-NoC topologies and routing algorithms. Challenges related to the switch from the 2D topologies to 3D ones should also be addressed as well as the challenges in applying 3D NoCs in real-time systems. Some relevant references follow.

Literatur/Dokumentation

• [1] B. S. Feero and P. P. Pande, "Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation," in IEEE Transactions on Computers, vol. 58, no. 1, pp. 32-45, Jan. 2009. doi: 10.1109/TC.2008.142
• [2] Michael Opoku Agyeman, Ali Ahmadinia, Alireza Shahrabi, Efficient routing techniques in heterogeneous 3D Networks-on-Chip, Parallel Computing, Volume 39, Issue 9, September 2013, Pages 389-407, ISSN 0167-8191, <link typo3 michael opoku ali alireza efficient routing techniques in heterogeneous parallel volume issue september pages issn http: dx.doi.org j.parco.2013.04.009.>dx.doi.org/10.1016/j.parco.2013.04.009.
• [3] Y. Qian, Z. Lu and W. Dou, "From 2D to 3D NoCs: A case study on worst-case communication performance," 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, San Jose, CA, 2009, pp. 555-562.
• [4] Feng, Chaochao, et al. "A low-overhead fault-aware deflection routing algorithm for 3D network-on-chip." 2011 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2011.