SAFURE - SAFety and secURity by dEsign for interconnected mixed-critical cyber-physical systems

Motivation

The current approach for security on safety-critical embedded systems is generally to keep subsystems separated, but this approach is now being challenged by technological evolution towards openness, increased communications and use of multi-core architectures. SAFURE will push forward the limits of current approaches on safety and security mixed-critical systems in a way that has never been done before.

Project Goals

SAFURE’s mission is to design a cyber-physical systems by implementing a methodology that ensures safety and security by construction. This methodology is enabled by a framework developed to extend system capabilities so as to control the concurrent effects of security threats on the system behavior. With this in mind, the project aims at allowing European suppliers of safety-critical embedded products to develop more cost and energy-aware solutions.

Project Consortium

The SAFURE project comprises 12 partners from 6 European countries:

Technikon Forschungs- und Planungsgesellschaft mbH, Villach, Austria
Escrypt GmbH Embedded Security, Bochum, Germany
Magneti Marelli S.P.A., Milano, Italy
TTTech Computertechnik AG, Vienna, Austria
Sysgo AG, Klein-Whinternheim, Germany
Symtavision GmbH, Braunschweig, Germany
Thales SA, Neuilly Sur Seine, France
Technische Universität Braunschweig, Braunschweig, Germany
Barcelona Supercomputing Center, Barcelona, Spain
Scuola Superiore Di Studi Universitari E Di Perfezionamento Sant'Anna, Pisa, Italy
Eidgenoessische Technische Hochschule Zürich, Zürich, Switzerland
Thales Communications & Security SAS, Gennevilliers, France

Role of the IDA

IDA will contribute to the SAFURE project in the increasingly important area of switched real-time networks. Specifically, methods and algorithms for safe mixed-critical communication over switched Ethernet (including IEEE 802.1Q (Standard Ethernet), IEEE 802.1Qav (Ethernet AVB), and IEEE 802.1Qbv (Ethernet TSN)) will be developed.

Contributions include:

Formal worst-case analysis methods for safe and timely message delivery
Support for mixed-critical traffic, e.g. via isolation or sufficient independence
Proactive network admission and congestion control, e.g. via Software Defined Networking (SDN)
Error and attack detection, prevention, containment, and recovery mechanisms, e.g. via ingress filtering and monitoring, and network reconfiguration (SDN mechanisms)

Further contributions include:

Analysis of the transport of legacy data (e.g. CAN) via gateways over an Ethernet backbone network
Weakly-hard transmission guarantees in multi-hop topologies (e.g. Ethernet)

Further information

For further information, please visit the project website at: www.safure.eu

Funding

This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 644080.

This work was supported by the Swiss State Secretariat for Education‚ Research and Innovation (SERI) under contract number 15.0025. The opinions expressed and arguments employed herein do not necessarily reflect the official views of the Swiss Government.

People at IDA

Daniel Thiele (email)

Robin Hofmann

Related Publications

The listed material is protected by copyright. The corresponding copyright must be observed.

Robin Hofmann, Borislav Nikolic and Rolf Ernst, "Challenges and Limitations of IEEE 802.1 CB-2017", , No. 12(4), pp. 105-108, April 2019.
@article{Hofmann2019ChallengesandLimitations, author = {Robin Hofmann and Borislav Nikolic and Rolf Ernst}, booktitle = {IEEE Embedded Systems Letters}, month = apr, pages = {105-108}, title = {{Challenges and Limitations of IEEE 802.1 CB-2017}}, number = {12(4)}, year = {2019} }
Haibo Zeng, Prachi Joshi, Daniel Thiele, Jonas Diemer, Philip Axer, Rolf Ernst and Petru Eles, "Handbook of Hardware/Software Codesign - Chapter: Networked Real-Time Embedded Systems"Soonhoi Ha and Jürgen Teich, Ed., Springer, 2017.
@inbook{electrical2017handbook, author = {Haibo Zeng and Prachi Joshi and Daniel Thiele and Jonas Diemer and Philip Axer and Rolf Ernst and Petru Eles}, editor = {Soonhoi Ha and Jürgen Teich, Ed.}, publisher = {Springer}, title = {{Handbook of Hardware/Software Codesign - Chapter: Networked Real-Time Embedded Systems}}, year = {2017} }
Daniel Thiele and Rolf Ernst, "Formal Worst-Case Performance Analysis of Time-Sensitive Ethernet with Frame Preemption" in Proceedings of Emerging Technologies and Factory Automation (ETFA), (Berlin, Germany), pp. 9, Januar 2016, BEST PAPER AWARD.
@inproceedings{thiele2016formal2, address = {Berlin, Germany}, author = {Daniel Thiele and Rolf Ernst}, booktitle = {Proceedings of Emerging Technologies and Factory Automation (ETFA)}, month = jan, note = {BEST PAPER AWARD}, pages = {9}, title = {{Formal Worst-Case Performance Analysis of Time-Sensitive Ethernet with Frame Preemption}}, year = {2016} }
Daniel Thiele and Rolf Ernst, "Formal Worst-Case Timing Analysis of Ethernet TSN’s Burst-Limiting Shaper" in Design Automation and Test in Europe (DATE), (Dresden, Germany), März 2016.
@inproceedings{thiele2016formal1, address = {Dresden, Germany}, author = {Daniel Thiele and Rolf Ernst}, booktitle = {Design Automation and Test in Europe (DATE)}, month = mar, title = {{Formal Worst-Case Timing Analysis of Ethernet TSN’s Burst-Limiting Shaper}}, year = {2016} }
Daniel Thiele and Rolf Ernst, "Formal Analysis Based Evaluation of Software Defined Networking for Time-Sensitive Ethernet" in Design Automation and Test in Europe (DATE), (Dresden, Germany), März 2016.
@inproceedings{thiele2016formal, address = {Dresden, Germany}, author = {Daniel Thiele and Rolf Ernst}, booktitle = {Design Automation and Test in Europe (DATE)}, month = mar, title = {{Formal Analysis Based Evaluation of Software Defined Networking for Time-Sensitive Ethernet}}, year = {2016} }
Daniel Thiele, Rolf Ernst and Jonas Diemer, "Formal Worst-Case Timing Analysis of Ethernet TSN’s Time-Aware and Peristaltic Shapers" in Vehicular Networking Conference (VNC), (Kyoto, Japan), Dezember 2015.
@inproceedings{thiele2015formalworstcase, address = {Kyoto, Japan}, author = {Daniel Thiele and Rolf Ernst and Jonas Diemer}, booktitle = {Vehicular Networking Conference (VNC)}, month = dec, title = {{Formal Worst-Case Timing Analysis of Ethernet TSN’s Time-Aware and Peristaltic Shapers}}, year = {2015} }
Daniel Thiele, Johannes Schlatow, Philip Axer and Rolf Ernst, "Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks (http://dx.doi.org/10.1007/s11241-015-9243-y)", Real-Time Systems, 2015.
@article{thiele2015formal, author = {Daniel Thiele and Johannes Schlatow and Philip Axer and Rolf Ernst}, journal = {Real-Time Systems}, title = {{Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks (http://dx.doi.org/10.1007/s11241-015-9243-y)}}, url = {http://dx.doi.org/10.1007/s11241-015-9243-y}, year = {2015} }
Daniel Thiele, Philip Axer and Rolf Ernst, "Improving Formal Timing Analysis of Switched Ethernet by Exploiting FIFO Scheduling" in Design Automation Conference (DAC), (San Francisco, CA, USA), Juni 2015.
@inproceedings{thiele2015improving, address = {San Francisco, CA, USA}, author = {Daniel Thiele and Philip Axer and Rolf Ernst}, booktitle = {Design Automation Conference (DAC)}, month = jun, title = {{Improving Formal Timing Analysis of Switched Ethernet by Exploiting FIFO Scheduling}}, year = {2015} }

SAFURE