Embedded systems can be found in nearly any part of our everyday life. They are also present in markets with highly specialized requirements like medical technology, the aerospace industry or the automotive domain including a lot of safety-critical systems. In the year 2000 98,2% of the CPUs produced were embedded system CPUs. The remaining 1,8% of the CPU production are shared between laptops, desktops and servers 1.
Analog the lines of the increasing requirements and expectations of the industry, complexity of embedded systems is increasing and the interactions between the several subsystems are getting more and more complicated. On the other hand the life cycle of a product and its design cycle abbreviate constantly because of a very high pressure of competition within the market. According to the International Technology Roadmap for Semiconductors in the year 2018 the design cycle for a SoC (system on chip) is going to be only 9 month instead of today’s 12 month 2.
It is possible to counteract the emerging time pressure by parallelization of the former sequential design steps. Thereby several hardware and software components are developed at the same time. This demands a very close collaboration and a good coordination of every single step. But within today’s system industry it has become the norm for the several components to be delivered by specialized suppliers. This fact leads to a development process that is distributed even across company boarders. Therefore the design data and properties of the subsystems have to be fixed at the earliest for they are needed as part of the contracts which regulate the collaboration. Most of the specifications generated in this phase are based on estimations which can be derived from know-how an expert knowledge of the employees because there are neither data nor any dependencies known in real terms.
The high complexity of the technical dependencies within the complete system on the one hand and the requested innovation during a constant cost reduction on the other hand are the main challenges of the development process. Because of parallelization, the following distribution across company boarders and the haunting of own interests by the participating companies problems within the coordination of the development process can be expected.
Therefore it is the objective of this interdisciplinary project to introduce flexibility to the development process and thereby improve it.
SAKE (Japanese: 酒; pronounced [sa.kɛ]) is actually the Japanese collective term for alcoholic beverages. Very often it is used especially for a culinary delicacy made from fermented rice.
At the IDA SAKE means „Systemanalyse und Koordination flexibler Entwicklungsprozesse für komplexe Eingebettete Systeme“ and stands for an interdisciplinary research project financed by the DFG (Deutsche Forschungsgemeinschaft).
Within the project four pivotal questions are addressed to provide the basis and solutions for the problem described above.
The first question considers the technical dependencies inside the development process. In this context design patterns have to be identified and subsequent dependencies have to be derived from these patterns. Within the second question reliability of the raw data as well as the resultant data have to be determined under a technical point of view. Of special interest are the effects which the properties of the several components and their interfaces have onto the overall result of the complete system. The third question deals with options for increasing business efficiency of the decentralized development process. For this, appropriate coordination mechanisms and incentive schemes will be developed, which guarantee that all partners behave conform to the overall objective. The fourth question requires a process model for integrative adoption in decentralized development projects to be developed. In this context, the acquired technical and economic relations will be integrated and applicability of the approach will be discussed.
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1 Tennenhouse, David. Proactive Computing. Communications of the ACM, page 43 - 50. May 2000, Volume 43, Issue 5.
2 International Technology Roadmap for Semiconductors 2005 Edition Design. [referenced january the 20th 2007].
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