Complex embedded systems affect our life every day. The electronic infrastructure of a car, for example, consists of 30 to 40 electronic control units, which are linked by busses like CAN and LIN. The development of such systems proves to be very difficult, time consuming and therefore, cost-intensive. Furthermore, complexity will even increase because of the customer’s demand for more features and safety. Hence the development of new extensive embedded systems is often evolutionary. You take an existing system and enhance it according to your new requirements.
In the early phases of such a design flow you have to draft a rough system-architecture. You have to decide what HW components and bus topology should be used and how you spread the functionality over the system. The final architecture should fulfil all requirements while keeping down costs.
The timing behaviour is one important requirement which becomes more and more relevant because of its impacts on the functionality of the whole system. Insufficient consideration of the timing could result in expensive re-design cycles. Hence the developer needs a methodology which helps him to find a rough system-architecture systematically and fast. Until today no satisfactory solution is available for such an early architecture exploration regarding the timing behaviour.
The vision of the project “wormhole” is to create such a methodology. Initially we focus on the single-process analysis. The execution time of SW components which are programmed for a special HW (A) should be predicted for another HW (B) (evolutionary design). Such a prediction is difficult because we are at the beginning of the design flow and we have no source code for the new target (B). Porting is no way out because it is very time and cost consuming even if you want to determine multiple targets. So we need a solution which is based on the characteristics of the source code or assembly running on the provided HW (A). Because we cannot run the SW on the target HW (B) we will lose accuracy. But this will be acceptable, if the imprecision is small enough, not to affect later design steps.