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  • ACCORD
    • Summary
    • The MpSoC Verification Gap
    • Methodology
    • Short Presentation
    • Conference Publications
    • Contributions to Journals and Books
    • Additional Publications

ACCORD


Summary

The ACCORD project addresses the Analysis of Multicore Communication and its Optimization in Real-time Devices. We are investigating a formal performance analysis approach and have applied it to various industrial examples.

The MpSoC Verification Gap

Fig. 1 From Distributed Systems to MPSoCs.

The transition of consumer products from SoC to MpSoC is driven by higher performance needs at low power consumption demands. Like in distributed embedded systems, multiprocessing comes at the cost of higher computation and communication complexity. Other than in distributed embedded systems, task communication is overlaid by memory traffic leading to very complex communication patterns including the effects of multithreading and non-blocking memory accesses.

Predicting the timing behaviour of such multiprocessor systems is fundamentally more difficult than in the single processor case: The interaction and correlation between distributed system components, such as a shared memory or coprocessors, makes it nearly impossible to uncover corner cases with purely simulative approaches. Memory accesses are highly dynamic and can routinely lead to overload situations which must be handled by communication mechanisms such as buffering and traffic shaping which have a feedback effect on task execution. It is very difficult if not impossible to systematically create corner cases for simulations that reliably trigger such situations. Even worse, memory access patterns are sensitive to changes in the software code which cannot be appropriately modelled in simulation. This makes it difficult to start system verification at early design phases and plan for later software updates. Thus, a risk remains that the system fails. This risk increases system complexity. Simulation alone simply is not appropriate any more.

Methodology

At our institute, we have developed a performance analysis tool, SymTA/S, and an appropriate design methodology. This framework can back up a simulation by supplying robust data on cornercase behaviour, and by allowing to quickly explore new design options. It is the basis of the commercial tool that is sold by the spin-off, SymtaVision.

The classic formal performance analysis approach is bottom-up: First, the individual task timing is derived in an isolated (and therefore controllable) environment. This can use simulation, tracing, emulation, or whatever is currently used in the design process. Secondly, this information is coupled with information about the local components (such as the scheduling behaviour and contextswitch times, caches) to derive the local execution behaviour. Finally, all system level influences (such as message delays, accesses to shared resources, or traffic shapers) are considered to produce the overall timing of the system.

This separation of concerns allows each level of abstraction to be investigated separately using more sophisticated methods than in unified approaches. The system level analysis step can quickly evaluate a given setup, identify corner cases and allow designers to optimize the system e.g. for performance or robustness.

Extended Task model and Analysis Framework

In MpSoC, the mentioned system level is entangled with the task level, in the sense that a task’s access to the shared memory is subject to system level influences. Thus, a timing feedback exists.We solve this technical problem by introduction of an extended task model that explicitly expresses shared resource accesses. An automatic iterative analysis derives the joint timing.

The extended task model is depicted in Fig. 1. In addition to the classical task states “ready” and “finished”, such a task is in the “waiting” state when it has initiated a “transaction” to a shared resource that supplies data or services that must be finished before the task may continue its execution.The response time of a task is then a composition of local and remote effects: Locally, its core execution time, the amount of local scheduling interference and the context switch times need to be considered; remotely, the transactions will experience network delay and interference on the shared resource/memory.The timing of the individual transactions is highly dynamic. In the case of thousands of memory accesses per task invocation, not every memory access can experience the worst case timing. Therefore, previous approaches which relied on worst-case assumptions, implied an unacceptably high overestimation. We have proposed to consider the timing of all transactions jointly, thereby assuming worst case interference on the transactions distributed over the task’s invocation.

Fig. 2 Extended Task Model.

Short Presentation

This is a short overview presentation recently held at an ArtistDesign project meeting in April 2009:

People involved at IDA

  • Simon Schliecker

Students

  • Axel von Engel (has investigated cache effects in his Studienarbeit)
  • Matthias Hanke (has looked into backward pressure issues)
  • Daniel Thiele (empirical investigation using VAST simulation framework)
  • Daniel Dömeland (investigates cache behavior)
  • Also, several former students have contributed to this project.

Conference Publications

The listed material is protected by copyright. The corresponding copyright must be observed.


Simon Schliecker, Mircea Negrean and Rolf Ernst, "Bounding the Shared Resource Load for the Performance Analysis of Multiprocessor Systems" in Proc. of Design, Automation, and Test in Europe (DATE), (Dresden, Germany), März 2010.

Show bibtex code: Bounding the Shared Resource Load for the Performance Analysis of Multiprocessor Systems Call website/url: http://www.google.com/url?sa=t&source=web&ct=res&cd=1&ved=0CAsQFjAA&url=http%3A%2F%2Fwww.date-conference.com%2Fproceedings%2FPAPERS%2F2010%2FDATE10%2FPDFFILES%2F06.6_4.PDF&ei=JpzWS4_lCobt-Ab15r2FBg&usg=AFQjCNE0tySJInhzjlFgmHb4tUD4_xVi4A&sig2=pHo3iouRXDIRuX3BaXtRdg

@inproceedings{SNE10:BoundShareResouPerfo,

address = {Dresden, Germany},
author = {Simon Schliecker and Mircea Negrean and Rolf Ernst},
booktitle = {Proc. of Design, Automation, and Test in Europe (DATE)},
month = mar,
title = {{Bounding the Shared Resource Load for the Performance Analysis of Multiprocessor Systems}},
url = {http://www.google.com/url?sa=t&source=web&ct=res&cd=1&ved=0CAsQFjAA&url=http%3A%2F%2Fwww.date-conference.com%2Fproceedings%2FPAPERS%2F2010%2FDATE10%2FPDFFILES%2F06.6_4.PDF&ei=JpzWS4_lCobt-Ab15r2FBg&usg=AFQjCNE0tySJInhzjlFgmHb4tUD4_xVi4A&sig2=pHo3iouRXDIRuX3BaXtRdg},
year = {2010}

}

Maarten Wiggers, Lothar Thiele, Edward A. Lee, Simon Schliecker and Marco Bekooij, "Modeling and analyzing real-time multiprocessor systems" in Proc. 8th Intl. Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), (Scottsdale, AZ), pp. 329-330, Oktober 2010.

Show bibtex code: Modeling and analyzing real-time multiprocessor systems Call website/url: http://portal.acm.org/citation.cfm?doid=1878961.1879019

@inproceedings{WTL+11:Modelanalyrealtmulti,

address = {Scottsdale, AZ},
author = {Maarten Wiggers and Lothar Thiele and Edward A. Lee and Simon Schliecker and Marco Bekooij},
booktitle = {Proc. 8th Intl. Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)},
month = oct,
pages = {329-330},
title = {{Modeling and analyzing real-time multiprocessor systems}},
url = {http://portal.acm.org/citation.cfm?doid=1878961.1879019},
year = {2010}

}

Mircea Negrean, Simon Schliecker and Rolf Ernst, "Response-Time Analysis of Arbitrarily Activated Tasks in Multiprocessor Systems with Shared Resources" in Proc. of Design, Automation, and Test in Europe (DATE), (Nice, France), April 2009.

Show bibtex code: Response-Time Analysis of Arbitrarily Activated Tasks in Multiprocessor Systems with Shared Resources Call website/url: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5090720

@inproceedings{NSE09:RespoAnalyArbitActiv,

address = {Nice, France},
author = {Mircea Negrean and Simon Schliecker and Rolf Ernst},
booktitle = {Proc. of Design, Automation, and Test in Europe (DATE)},
month = apr,
title = {{Response-Time Analysis of Arbitrarily Activated Tasks in Multiprocessor Systems with Shared Resources}},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5090720},
year = {2009}

}

Simon Schliecker and Rolf Ernst, "A Recursive Approach to End-To-End Path Latency Computation in Heterogeneous Multiprocessor Systems" in Proc. 7th International Conference on Hardware Software Codesign and System Synthesis (CODES-ISSS), (Grenoble, France), ACM, Oktober 2009.

Show bibtex code: A Recursive Approach to End-To-End Path Latency Computation in Heterogeneous Multiprocessor Systems Display/download pdf-file: SE09_RecurApproEndToLaten.pdf Call website/url: http://doi.acm.org/10.1145/1629435.1629494

@inproceedings{SE09:RecurApproEndToLaten,

address = {Grenoble, France},
author = {Simon Schliecker and Rolf Ernst},
booktitle = {Proc. 7th International Conference on Hardware Software Codesign and System Synthesis (CODES-ISSS)},
month = oct,
organization = {ACM},
title = {{A Recursive Approach to End-To-End Path Latency Computation in Heterogeneous Multiprocessor Systems}},
url = {http://doi.acm.org/10.1145/1629435.1629494},
year = {2009}

}

Simon Schliecker, Arne Hamann, Razvan Racu and Rolf Ernst, "Formal Methods for System Level Performance Analysis and Optimization" in Proc. of the Design Verification Conference (DVCon), (San José, CA), Februar 2008.

Show bibtex code: Formal Methods for System Level Performance Analysis and Optimization Call website/url: http://www.digibib.tu-bs.de/?docid=00028094

@inproceedings{SHR+08:FormaMethoSysteLevel,

address = {San José, CA},
author = {Simon Schliecker and Arne Hamann and Razvan Racu and Rolf Ernst},
booktitle = {Proc. of the Design Verification Conference (DVCon)},
month = feb,
title = {{Formal Methods for System Level Performance Analysis and Optimization}},
url = {http://www.digibib.tu-bs.de/?docid=00028094},
year = {2008}

}

Simon Schliecker, Mircea Negrean, Gabriela Nicolescu, Pierre Paulin and Rolf Ernst, "Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip" in Proc. 6th International Conference on Hardware Software Codesign and System Synthesis (CODES-ISSS), (Atlanta, GA), Oktober 2008.

Show bibtex code: Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip Call website/url: http://doi.acm.org/10.1145/1450135.1450172

@inproceedings{SNN+08:ReliaPerfoAnalyMulti,

address = {Atlanta, GA},
author = {Simon Schliecker and Mircea Negrean and Gabriela Nicolescu and Pierre Paulin and Rolf Ernst},
booktitle = {Proc. 6th International Conference on Hardware Software Codesign and System Synthesis (CODES-ISSS)},
month = oct,
title = {{Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip}},
url = {http://doi.acm.org/10.1145/1450135.1450172},
year = {2008}

}

Simon Schliecker, Jonas Rox, Matthias Ivers and Rolf Ernst, "Providing Accurate Event Models for the Analysis of Heterogeneous Multiprocessor Systems" in Proc. 6th International Conference on Hardware Software Codesign and System Synthesis (CODES-ISSS), (Atlanta, GA), Oktober 2008.

Show bibtex code: Providing Accurate Event Models for the Analysis of Heterogeneous Multiprocessor Systems Display/download pdf-file: SRIetal08_ProviAccurEventModel.pdf Call website/url: http://doi.acm.org/10.1145/1450135.1450177

@inproceedings{SRI+08:ProviAccurEventModel,

address = {Atlanta, GA},
author = {Simon Schliecker and Jonas Rox and Matthias Ivers and Rolf Ernst},
booktitle = {Proc. 6th International Conference on Hardware Software Codesign and System Synthesis (CODES-ISSS)},
journal = {Proc. 5th International Conference on Hardware Software Codesign and System Synthesis (CODES-ISSS)},
month = oct,
title = {{Providing Accurate Event Models for the Analysis of Heterogeneous Multiprocessor Systems}},
url = {http://doi.acm.org/10.1145/1450135.1450177},
year = {2008}

}

Simon Perathoner, Ernesto Wandeler, Lothar Thiele, Arne Hamann, Simon Schliecker, Rafik Henia, Razvan Racu, Rolf Ernst and Michael González Harbour, "Influence of Different System Abstractions on the Performance Analysis of Distributed Real-Time Systems" in Proc. ACM Conference on Embedded Software (EMSOFT), (Salzburg, Austria), Oktober 2007.

Show bibtex code: Influence of Different System Abstractions on the Performance Analysis of Distributed Real-Time Systems Call website/url: http://doi.acm.org/10.1145/1289927.1289959

@inproceedings{PWT+07:InfluDiffeSysteAbstr,

address = {Salzburg, Austria},
author = {Simon Perathoner and Ernesto Wandeler and Lothar Thiele and Arne Hamann and Simon Schliecker and Rafik Henia and Razvan Racu and Rolf Ernst and Michael González Harbour},
booktitle = {Proc. ACM Conference on Embedded Software (EMSOFT)},
journal = {Proc. ACM Conference on Embedded Software (EMSOFT)},
month = oct,
title = {{Influence of Different System Abstractions on the Performance Analysis of Distributed Real-Time Systems}},
url = {http://doi.acm.org/10.1145/1289927.1289959},
year = {2007}

}

Simon Schliecker, Matthias Ivers, Jan Staschulat and Rolf Ernst, "A Framework for the Busy Time Calculation of Multiple Correlated Events" in 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, No. 06902, (Dresden, Germany), Juli 2006.

Show bibtex code: A Framework for the Busy Time Calculation of Multiple Correlated Events Display/download pdf-file: SISetal06_FrameCalcuMultiCorre.pdf Call website/url: http://drops.dagstuhl.de/opus/volltexte/2006/676/

@inproceedings{SIS+06:FrameCalcuMultiCorre,

address = {Dresden, Germany},
author = {Simon Schliecker and Matthias Ivers and Jan Staschulat and Rolf Ernst},
booktitle = {6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis},
month = jul,
title = {{A Framework for the Busy Time Calculation of Multiple Correlated Events}},
url = {http://drops.dagstuhl.de/opus/volltexte/2006/676/},
number = {06902},
year = {2006}

}

Simon Schliecker, Matthias Ivers and Rolf Ernst, "Memory Access Patterns for the Analysis of MPSoCs" in North-East Workshop on Circuits and Systems, (Gatineau, Canada), IEEE, IEEE, Juni 2006.

Show bibtex code: Memory Access Patterns for the Analysis of MPSoCs Call website/url: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4016974

@inproceedings{SIE06:MemorAccesPatteAnaly,

address = {Gatineau, Canada},
author = {Simon Schliecker and Matthias Ivers and Rolf Ernst},
booktitle = {North-East Workshop on Circuits and Systems},
month = jun,
organization = {IEEE},
publisher = {IEEE},
title = {{Memory Access Patterns for the Analysis of MPSoCs}},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4016974},
year = {2006}

}

Simon Schliecker, Matthias Ivers and Rolf Ernst, "Integrated Analysis of Communicating Tasks in MPSoCs" in Proc. 3rd International Conference on Hardware Software Codesign and System Synthesis (CODES-ISSS), (Seoul, Korea), Oktober 2006.

Show bibtex code: Integrated Analysis of Communicating Tasks in MPSoCs Call website/url: http://doi.acm.org/10.1145/1176254.1176325

@inproceedings{SIE06:IntegAnalyCommuTasks,

address = {Seoul, Korea},
author = {Simon Schliecker and Matthias Ivers and Rolf Ernst},
booktitle = {Proc. 3rd International Conference on Hardware Software Codesign and System Synthesis (CODES-ISSS)},
month = oct,
title = {{Integrated Analysis of Communicating Tasks in MPSoCs}},
url = {http://doi.acm.org/10.1145/1176254.1176325},
year = {2006}

}

Jan Staschulat, Simon Schliecker, Matthias Ivers and Rolf Ernst, "Analysis of Memory Latencies in Multi-Processor Systems" in 5th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis, (Palma de Mallorca, Spain), Juli 2005.

Show bibtex code: Analysis of Memory Latencies in Multi-Processor Systems Display/download pdf-file: SSIetal05_AnalyMemorLatenMulti.pdf Call website/url: http://drops.dagstuhl.de/opus/volltexte/2007/813/

@inproceedings{SSI+05:AnalyMemorLatenMulti,

address = {Palma de Mallorca, Spain},
author = {Jan Staschulat and Simon Schliecker and Matthias Ivers and Rolf Ernst},
booktitle = {5th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis},
month = jul,
title = {{Analysis of Memory Latencies in Multi-Processor Systems}},
url = {http://drops.dagstuhl.de/opus/volltexte/2007/813/},
year = {2005}

}

Jan Staschulat, Simon Schliecker and Rolf Ernst, "Scheduling Analysis of Real-time Systems with Precise Modeling of Cache Related Preemption Delay" in Euromicro Conference on Real-Time Systems (ECRTS), (Palma de Mallorca, Spain), Juli 2005.

Show bibtex code: Scheduling Analysis of Real-time Systems with Precise Modeling of Cache Related Preemption Delay Call website/url: http://doi.ieeecomputersociety.org/10.1109/ECRTS.2005.26

@inproceedings{SSE05:SchedAnalyRealtSyste,

address = {Palma de Mallorca, Spain},
author = {Jan Staschulat and Simon Schliecker and Rolf Ernst},
booktitle = {Euromicro Conference on Real-Time Systems (ECRTS)},
month = jul,
title = {{Scheduling Analysis of Real-time Systems with Precise Modeling of Cache Related Preemption Delay}},
url = {http://doi.ieeecomputersociety.org/10.1109/ECRTS.2005.26},
year = {2005}

}

Contributions to Journals and Books

The listed material is protected by copyright. The corresponding copyright must be observed.


Simon Schliecker and Rolf Ernst, "Real-Time Performance Analysis of Multiprocessor Systems with Shared Memory", ACM Transactions on Embedded Computing Systems (Special Issue on Model Driven Embedded System Design), vol. 10-2, No. 22, Dezember 2010.

Show bibtex code: Real-Time Performance Analysis of Multiprocessor Systems with Shared Memory Call website/url: http://dx.doi.org/10.1145/1880050.1880058

@article{SE10:RealTPerfoAnalyMulti,

author = {Simon Schliecker and Rolf Ernst},
journal = {ACM Transactions on Embedded Computing Systems (Special Issue on Model Driven Embedded System Design)},
month = dec,
title = {{Real-Time Performance Analysis of Multiprocessor Systems with Shared Memory}},
url = {http://dx.doi.org/10.1145/1880050.1880058},
volume = {10-2},
year = {2010}

}

Simon Schliecker, Mircea Negrean and Rolf Ernst, "Response Time Analysis in Multicore ECUs with Shared Resources", IEEE Transactions on Industrial Informatics, vol. 5, No. 4, November 2009.

Show bibtex code: Response Time Analysis in Multicore ECUs with Shared Resources Call website/url: http://ieee-ies.org/tii/issues/iit09_4.shtml

@article{Sch09:RespoAnalyMultiShare,

author = {Simon Schliecker and Mircea Negrean and Rolf Ernst},
journal = {IEEE Transactions on Industrial Informatics},
month = nov,
title = {{Response Time Analysis in Multicore ECUs with Shared Resources}},
url = {http://ieee-ies.org/tii/issues/iit09_4.shtml},
volume = {5},
year = {2009}

}

Simon Schliecker, Jonas Rox, Rafik Henia, Razvan Racu, Arne Hamann and Rolf Ernst, "Formal Performance Analysis for Real-Time Heterogeneous Embedded Systems", in Model-Based Design of Heterogeneous Embedded Systems (Gabriela Nicolescu and Pieter J Mosterman, Ed.), chapter 3, pp. 57-92, CRC Press, November 2009.

Show bibtex code: Formal Performance Analysis for Real-Time Heterogeneous Embedded Systems Call website/url: http://www.crcpress.com/product/isbn/9781420067842

@incollection{SRH+08:ModelDesigHeterEmbed,

author = {Simon Schliecker and Jonas Rox and Rafik Henia and Razvan Racu and Arne Hamann and Rolf Ernst},
booktitle = {Model-Based Design of Heterogeneous Embedded Systems},
chapter = {3},
editor = {Gabriela Nicolescu and Pieter J Mosterman, Ed.},
month = nov,
pages = {57-92},
publisher = {CRC Press},
series = {tational Analysis, Synthesis, and Design of Dynamic Systems},
title = {{Formal Performance Analysis for Real-Time Heterogeneous Embedded Systems}},
url = {http://www.crcpress.com/product/isbn/9781420067842},
year = {2009}

}

Simon Schliecker, Jonas Rox, Mircea Negrean, Kai Richter, Marek Jersak and Rolf Ernst, "System Level Performance Analysis for Real-Time Automotive Multi-Core and Network Architectures", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, No. 7, pp. 979-992, Juli 2009.

Show bibtex code: System Level Performance Analysis for Real-Time Automotive Multi-Core and Network Architectures Call website/url: http://dx.doi.org/10.1109/TCAD.2009.2013286

@article{SRN+08:SysteLevelPerfoAnaly,

author = {Simon Schliecker and Jonas Rox and Mircea Negrean and Kai Richter and Marek Jersak and Rolf Ernst},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
month = jul,
pages = {979-992},
title = {{System Level Performance Analysis for Real-Time Automotive Multi-Core and Network Architectures}},
url = {http://dx.doi.org/10.1109/TCAD.2009.2013286},
volume = {28},
year = {2009}

}

Simon Perathoner, Ernesto Wandeler, Lothar Thiele, Arne Hamann, Simon Schliecker, Rafik Henia, Razvan Racu, Rolf Ernst and Michael González Harbour, "Influence of different abstractions on the performance analysis of distributed hard real-time systems", Journal Design Automation for Embedded Systems (available as online first, April 2008), vol. 13, No. 1, pp. 27-49, Juni 2009.

Show bibtex code: Influence of different abstractions on the performance analysis of distributed hard real-time systems Call website/url: http://dx.doi.org/10.1007/s10617-008-9015-1

@article{PWT+08:Infludiffeabstrperfo,

author = {Simon Perathoner and Ernesto Wandeler and Lothar Thiele and Arne Hamann and Simon Schliecker and Rafik Henia and Razvan Racu and Rolf Ernst and Michael González Harbour},
journal = {Journal Design Automation for Embedded Systems (available as online first, April 2008)},
month = jun,
pages = {27-49},
title = {{Influence of different abstractions on the performance analysis of distributed hard real-time systems}},
url = {http://dx.doi.org/10.1007/s10617-008-9015-1},
volume = {13},
year = {2009}

}

Additional Publications

The listed material is protected by copyright. The corresponding copyright must be observed.


Daniel Thiele, "Empirische Untersuchung des Timings von Speicherzugriffen in Multiprozessorsystemen", Studienarbeit, Institute of Computer and Network Engineering, Technische Universität Braunschweig, November 2008.
IDA-Signatur: STA 3377

Show bibtex code: Empirische Untersuchung des Timings von Speicherzugriffen in Multiprozessorsystemen

@masterthesis{Thi08:EmpirUnterTiminSpeic,

author = {Daniel Thiele},
howpublished = {Studienarbeit},
institution = {Technische Universität Braunschweig},
month = nov,
title = {{Empirische Untersuchung des Timings von Speicherzugriffen in Multiprozessorsystemen}},
type = {Studienarbeit},
year = {2008}

}

Simon Schliecker, Mircea Negrean and Rolf Ernst, "Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip (with appendix)", No. 22837, Technische Universität Braunschweig, 2008.

Show bibtex code: Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip (with appendix) Call website/url: http://www.digibib.tu-bs.de/?docid=00022837

@techreport{SNE08:ReliaPerfoAnalyMulti,

author = {Simon Schliecker and Mircea Negrean and Rolf Ernst},
institution = {Technische Universität Braunschweig},
title = {{Reliable Performance Analysis of a Multicore Multithreaded System-On-Chip (with appendix)}},
url = {http://www.digibib.tu-bs.de/?docid=00022837},
number = {22837},
year = {2008}

}

Simon Schliecker and Rolf Ernst, "Compositional Path Latency Computation with Local Busy Times", No. IDA-08-01, Technical University Braunschweig, Braunschweig, Germany, Januar 2008.

Show bibtex code: Compositional Path Latency Computation with Local Busy Times Display/download pdf-file: SE08_CompoLatenCompuLocal.pdf

@techreport{SE08:CompoLatenCompuLocal,

address = {Braunschweig, Germany},
author = {Simon Schliecker and Rolf Ernst},
institution = {Technical University Braunschweig},
month = jan,
title = {{Compositional Path Latency Computation with Local Busy Times}},
number = {IDA-08-01},
year = {2008}

}

Mircea Negrean, "Analytical Performance Evaluation of an ST Microelectronics Multiprocessing Platform", Master Thesis, Technische Universität Braunschweig, Germany, Mai 2007.
IDA-Signatur: MA 5

Show bibtex code: Analytical Performance Evaluation of an ST Microelectronics Multiprocessing Platform

@masterthesis{Neg07:AnalyPerfoEvaluMicro,

address = {Germany},
author = {Mircea Negrean},
month = may,
school = {Technische Universität Braunschweig},
title = {{Analytical Performance Evaluation of an ST Microelectronics Multiprocessing Platform}},
type = {Master Thesis},
year = {2007}

}

Simon Schliecker, Matthias Ivers and Rolf Ernst, "A Proof for Memory Access Patterns for the Analysis of MPSoCs", No. IDA-2006-01, Institute for Computer and Communication Network Engineering, Braunschweig, Germany, April 2006, This TR contains a supplement proof for.

Show bibtex code: A Proof for Memory Access Patterns for the Analysis of MPSoCs Display/download pdf-file: SIE06_ProofMemorAccesPatte.pdf

@techreport{SIE06:ProofMemorAccesPatte,

address = {Braunschweig, Germany},
author = {Simon Schliecker and Matthias Ivers and Rolf Ernst},
institution = {Institute for Computer and Communication Network Engineering},
month = apr,
note = {This TR contains a supplement proof for},
title = {{A Proof for Memory Access Patterns for the Analysis of MPSoCs}},
type = {Technical Report},
number = {IDA-2006-01},
year = {2006}

}

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