Computer-Aided Design of Digital Circuits

This Lab will take place in the winter term and in the summer term. The registration to this lab is organized via StudIP (see the link mentioned above). Start of registration is the 13.03.2023, 10:00.

Important: Due to high demand and limited places, there can be colloquia for entry to the course.

This lab is well suited for English speaking students.

There will be 15 participants working in groups of 3. The grouping will be performed later. Participation is mandatory.

This lab "Computer-Aided Design of Digital Circuits" focuses on the design and implemementation of a game of PONG. The FPGA-Chip (Field Programmable Gate Array) that is to be designed, will be a crucial part of the controls for the game.

The hardware description language VHDL (Very High Speed Integrated Circuit Hardware Description Language) will be used as specification and implementation language.
A short introduction to VHDL that will ease the mastering of this lab is available for download (see below).

For the simulation and synthesis of a hardware description, the tools ModelSim and Xilinx ISE will be used. A short guide to these tools (as well as an introductory tutorial) is available for download as well. 

Concluding the lab, not only a download file for the Xilinx FPGA, but also a fully functional PONG game according to its specification was developed.