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  • Computer-Aided Design of Digital Circuits
    • Registration
    • Number of participants
    • Short description
    • Scripts

Computer-Aided Design of Digital Circuits


Name: Rechnergestützter Entwurf digitaler Schaltungen
Type: Practical course
Lecturer: Jonas Peeck, Nora Sperling
Term: Summer and winter term
Date: Donnerstag 13:15 - 16:15
Semester hours: 4
Examination type: N/A
StudIP Link: https://studip.tu-braunschweig.de/...

Registration

This Lab will take place in the winter term and in the summer term. The registration to this lab is organized via StudIP (see the link mentioned above). Start of registration is the 13.03.2023, 10:00.

Important: Due to high demand and limited places, there can be colloquia for entry to the course.

This lab is well suited for English speaking students.



Number of participants

There will be 15 participants working in groups of 3. The grouping will be performed later. Participation is mandatory.


Short description

This lab "Computer-Aided Design of Digital Circuits" focuses on the design and implemementation of a game of PONG. The FPGA-Chip (Field Programmable Gate Array) that is to be designed, will be a crucial part of the controls for the game.

 

The hardware description language VHDL (Very High Speed Integrated Circuit Hardware Description Language) will be used as specification and implementation language.
A short introduction to VHDL that will ease the mastering of this lab is available for download (see below).

For the simulation and synthesis of a hardware description, the tools ModelSim and Xilinx ISE will be used. A short guide to these tools (as well as an introductory tutorial) is available for download as well. 

Concluding the lab, not only a download file for the Xilinx FPGA, but also a fully functional PONG game according to its specification was developed.


Scripts

 

Script

 

Postscript

 

Postscript, gzip

 

PDF

VDHL Grundlagen für das Praktikum (Englisch)     150 KB
Einführung in VHDL (Deutsch)

650 KB

140 KB 340 KB
VHDL Kompact (Uni Hamburg; Deutsch)     644 KB
Introduction to VHDL (Englisch)     8.9 MB

VHDL online tutorial (Deutsch und Englisch)

     
ModelSim Quick Guide     50 KB
Xilinx ISE 8.2i Software Manuals and Help (Englisch)     503 KB
Xilinx ISE Tutorial (Englisch)     130 KB
Xilinx Design Whitepaper (Englisch)     239 KB
Praktikum Skript (alle Aufgaben, Englisch)     ---
Praktikumsübersicht (Englisch)     689 KB
Übungen 1-13     Download
Digilent Adept HowTo (Englisch)     Download
       

Contact

Institute of Computer and Network Engineering
Hans-Sommer-Street 66
38106 Braunschweig
Phone: +49 (0)531 391-3734
Fax: +49 (0)531 391-4587

Office hours:

Mon: 
10:15-11:30 and 14:00-15:00
Tue:   
10:15-11:30 and 14:00-15:00
Wed:   
14:00-15:00
Thu: 
10:15-11:30 and 14:00-15:00
Fri:
10:15-11:30 and 14:00-15:00
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